IP Library › Granted Patent US 12,056,027
Granted Patent B2
US 12,056,027 · App. 17/949,287 · Granted Aug 6, 2024

Memory system and data processing system including the same

Inventors: Eung-Bo Shim (Gyeonggi-do, KR); Hyung-Sup Kim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F11/2094G06F11/073G06F11/076G06F11/1658G06F11/20G06F11/3037G06F11/326G11C29/08G11C29/42G11C29/4401G11C29/52G11C29/765G11C29/81G11C29/832G06F2201/82G11C2029/4402
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Quick Facts
Patent No.
US 12,056,027
App. No.
17/949,287
Granted
Aug 6, 2024
Kind
B2
Abstract

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Claims (13)

1. A data processing system comprising:

a plurality of memory systems and a compute system,

wherein each of the plurality of memory systems includes:

a plurality of memory devices each configured to store data, correct an error of the data and generate first error information including error details, and

a controller configured to acquire the first error information from the plurality of memory devices and generate second error information based on plural pieces of first error information received from the plurality of memory devices; and

wherein the compute system analyzes the second error information received from the plurality of memory systems.

2. The data processing system of claim 1 ,

wherein when an uncorrectable error occurred in a memory device included in a first memory device among the plurality of memory systems, a controller included of a first memory system provides a fatal signal to the compute system, and

wherein the compute system shuts down the first memory system in response to the fatal signal.

3. The data processing system of claim 1 ,

wherein each of the plurality of memory devices further includes a serial presence detect (SPD) component including characteristic data,

wherein the error details include manufacturing information included in characteristic data of a memory device which an error occurred, and

wherein the compute system extracts the manufacturing information from error details of the second error information, categorizes the second error information according to the manufacturing information and analyzes the categorized second error information.

Priority Claims (4)
KR 10-2017-0143428 · Oct 31, 2017 · national
KR 10-2017-0148004 · Nov 8, 2017 · national
KR 10-2018-0004390 · Jan 12, 2018 · national
KR 10-2019-0005161 · Jan 15, 2019 · national
Continuity (6)
Division 16851660 · Apr 17, 2020
Continuation In Part 16189984 · Nov 13, 2018
Continuation In Part 16674935 · Nov 5, 2019
Continuation In Part 16041258 · Jul 20, 2018
Continuation In Part 16039220 · Jul 18, 2018
Related Publication 20230015404A1 · Jan 19, 2023