SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

1 . A semiconductor device, comprising:

a substrate having a trench; and

a gate structure in the trench, wherein the gate structure comprising:

a lower gate electrode;

an upper gate electrode disposed over the lower gate electrode; and

a silicide layer contacting the upper gate electrode.

2 . The semiconductor device of claim 1 , further comprising:

a metal layer disposed between the lower gate electrode and the upper gate electrode;

wherein the silicide layer is formed along an interface between the metal layer and the upper gate electrode.

3 . The semiconductor device of claim 2 , wherein the upper gate electrode is separated from the lower gate electrode by the metal layer and the silicide layer.

4 . The semiconductor device of claim 1 , further comprising:

a lower dielectric layer disposed between the lower gate electrode and the substrate; and

a metal layer disposed between the lower dielectric layer and the upper gate electrode;

wherein the upper gate electrode is separated from the lower dielectric layer by the metal layer and the silicide layer.

5 . The semiconductor device of claim 4 , wherein the silicide layer contacts the lower dielectric layer.

6 . The semiconductor device of claim 4 , further comprising:

a barrier layer disposed between the lower gate electrode and the substrate;

wherein the barrier layer contacts the lower dielectric layer.

7 . The semiconductor device of claim 5 , further comprising:

an upper dielectric layer disposed between the upper gate electrode and the lower dielectric layer;

wherein the upper gate electrode is separated from the lower gate electrode by the upper dielectric layer, the metal layer, and the silicide layer.

8 . The semiconductor device of claim 7 , wherein the silicide layer contacts the upper dielectric layer.

9 . The semiconductor device of claim 1 , wherein the lower gate electrode and the upper gate electrode are configured to receive different voltages.

10 . The semiconductor device of claim 1 , wherein the gate structure is disposed in an active region of the substrate.

11 . The semiconductor device of claim 1 , wherein the gate structure is disposed in an isolation region of the substrate.

12 . A semiconductor device, comprising:

a substrate having a trench; and

a gate structure in the trench, wherein the gate structure comprising:

a lower gate electrode;

an upper gate electrode disposed over the lower gate electrode; and

a metal layer disposed between the lower gate electrode and the upper gate electrode.

13 . The semiconductor device of claim 12 , wherein the upper gate electrode is surrounded by the metal layer.

14 . The semiconductor device of claim 12 , further comprising:

a lower dielectric layer disposed between the lower gate electrode and the substrate;

wherein the metal layer is disposed between the lower dielectric layer and the upper gate electrode.

15 . The semiconductor device of claim 14 , further comprising:

an upper dielectric layer disposed between the upper gate electrode and the lower dielectric layer;

wherein the metal layer contacts the upper dielectric layer.

16 . The semiconductor device of claim 12 , further comprising:

a barrier layer disposed between the lower gate electrode and the substrate;

wherein the metal layer contacts the barrier layer.

17 . A method of manufacturing a semiconductor device, comprising:

forming a trench in a substrate;

disposing a lower gate electrode in the trench;

disposing a metal layer over the lower gate electrode; and

disposing an upper gate electrode over the metal layer.

18 . The method of claim 17 , further comprising:

forming a suicide layer along an interface between the metal layer and the upper gate electrode;

wherein the metal layer is formed by an atomic layer deposition (ALD) process.

19 . The method of claim 17 , wherein the metal layer is formed by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, and the metal layer is partially removed after the CVD process or PVD process to form a recessing portion for disposing the upper gate electrode.

20 . The method of claim 17 , further comprising:

forming a lower dielectric layer in the trench, wherein the lower gate electrode is spaced apart from the substrate by the lower dielectric layer;

disposing a barrier layer in the trench, wherein the lower gate electrode is spaced apart from the substrate by the barrier layer; and

forming an upper dielectric layer in the trench, wherein the upper dielectric layer contacts the barrier layer and the lower dielectric layer.