Providing multiple error correction code protection levels in memory

1. A method to operate a memory device, comprising:

generating, by an encoding unit of a memory device, a first codeword for a first error correction code (ECC) protection level;

performing, by a decoding unit of the memory device, an ECC operation on the first codeword at the first ECC protection level, wherein the decoding unit includes a first matrix, a second matrix, and a AND logic gate;

generating, by the encoding unit, a second codeword for a second ECC protection level; and

performing, by the decoding unit, an ECC operation on the second codeword at the second ECC protection level; and

the method includes performing the ECC operation on the first codeword at the first ECC protection level and performing the ECC operation on the second codeword at the second ECC protection level using the first matrix, the second matrix, and the AND logic gate, wherein performing the ECC operation on the second codeword at the second ECC protection level includes:

performing algebraic operations on the second codeword using the first matrix and the second matrix;

inputting a result of the algebraic operations into a first input of the AND logic gate; and

inputting, into a second input of the AND logic gate, an input indicating to perform the ECC operation on the second codeword at the second ECC protection level.

2. The method of claim 1 , wherein:

the first ECC protection level comprises an ECC correction capability of one data bit; and

the second ECC protection level comprises an ECC correction capability of two data bits.

3. The method of claim 1 , wherein the method includes:

generating the first codeword using payload data stored in a plurality of memory cells of the memory device and additional payload data stored in unused parity cells of the memory device; and

generating the second codeword using the payload data but not the additional payload data.

4. The method of claim 1 , wherein the method includes:

generating the first codeword using payload data stored in a plurality of memory cells of the memory device and additional payload data stored in unused parity cells of the memory device; and

generating the second codeword using the payload data and the additional payload data, wherein the additional payload data is set to zero while generating the parity data of the second codeword.

5. The method of claim 1 , wherein the method includes generating the first codeword and the second codeword using payload data stored in a plurality of memory cells of the memory device but not additional payload data stored in unused parity cells of the memory device.

6. A memory device, comprising:

an array of memory cells; and

an operating circuit for managing operation of the array, the operating circuit configured to:

generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, the codeword comprising:

payload data stored in a plurality of memory cells of the array; and

parity data associated with the payload data stored in parity cells of the array; and

perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level;

wherein the operating circuit includes a first matrix, a second matrix, and a AND logic gate; and

the operating circuit is configured to perform the ECC operation on the codeword at the first ECC protection level and the second ECC protection level using the first matrix, the second matrix, and the AND logic gate, wherein the operating circuit is configured to perform the ECC operation on the codeword at the first ECC protection level by:

performing algebraic operations on the codeword using the first matrix and the second matrix;

inputting a result of the algebraic operations into a first input of the AND logic gate; and

inputting, into a second input of the AND logic gate, an input indicating to perform the ECC operation at the first ECC protection level.

7. The memory device of claim 6 , wherein:

the parity data comprises a first number of parity bits stored in a first number of parity cells of the array upon the operating circuit generating the codeword for the first ECC protection level; and

the parity data comprises a second number of parity bits stored in a second number of parity cells of the array upon the operating circuit generating the codeword for the second ECC protection level.

8. The memory device of claim 6 , wherein:

the operating circuit includes three additional matrices; and

the operating circuit is configured to:

generate the parity data of the codeword for the first ECC protection level using each of the three additional matrices; and

generate the parity data of the codeword for the second ECC protection level using only two of the three additional matrices.

9. The memory device of claim 6 , wherein the operating circuit is configured to perform the ECC operation on the codeword at the second ECC protection level by:

performing algebraic operations on the codeword using the first matrix and the second matrix;

inputting a result of the algebraic operations into a first input of the AND logic gate; and

inputting, into a second input of the AND logic gate, an input indicating to perform the ECC operation at the second ECC protection level.

10. A memory device, comprising:

an array of memory cells; and

an operating circuit for managing operation of the array, the operating circuit configured to:

generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, the codeword comprising:

payload data stored in a plurality of memory cells of the array; and

parity data associated with the payload data stored in parity cells of the array; and

perform an ECC operation on the codeword at the first ECC protection level upon the operating circuit generating the codeword for the first ECC protection level; and

perform an ECC operation on the codeword at the second ECC protection level upon the operating circuit generating the codeword for the second ECC protection level;

wherein the operating circuit includes a first matrix, a second matrix, and a multiplexer; and

the operating circuit is configured to perform the ECC operation on the codeword at the first ECC protection level and the ECC operation on the codeword at the second ECC protection level using the first matrix, the second matrix, and the multiplexer, wherein the operating circuit is configured to perform the ECC operation on the codeword at the first ECC protection level by:

performing a first algebraic operation on the codeword using the first matrix and a second algebraic operation on the codeword using the second matrix;

performing a cubing operation on a result of the first algebraic operation;

inputting a result of the cubing operation into a first input of the multiplexer;

inputting a result of the second algebraic operation into a second input of the multiplexer; and

inputting an input indicating to perform the ECC operation at the first ECC protection level into a third input of the multiplexer.

11. The memory device of claim 10 , wherein the codeword comprises additional payload data stored in unused parity cells of the array upon the unit operating circuit generating the codeword for the first ECC protection level.

12. The memory device of claim 10 , wherein the operating circuit is configured to perform the ECC operation on the codeword at the second ECC protection level by:

performing a first algebraic operation on the codeword using the first matrix and a second algebraic operation on the codeword using the second matrix;

performing a cubing operation on a result of the first algebraic operation;

inputting a result of the cubing operation into a first input of the multiplexer;

inputting a result of the second algebraic operation into a second input of the multiplexer; and

inputting an input indicating to perform the ECC operation at the second ECC protection level into a third input of the multiplexer.

13. The memory device of claim 10 , wherein the parity data of the codeword for the first ECC protection level and the parity data of the codeword for the second ECC protection level comprise the same parity data.

14. A system, comprising:

a host device; and

a memory device comprising an array of memory cells and an operating circuit for managing operation of the array, the operating circuit configured to:

generate a codeword for a plurality of error correction code (ECC) protection levels, the codeword comprising:

payload data stored in a plurality of memory cells of the array; and

parity data associated with the payload data stored in parity cells of the array; and

perform an ECC operation on the codeword at the plurality of ECC protection levels;

wherein the operating circuit includes a first matrix, a second matrix, and a multiplexer; and

the operating circuit is configured to perform the ECC operation on the codeword at the plurality of ECC protection levels using the first matrix, the second matrix, and the multiplexer, wherein the operating circuit is configured to perform the ECC operation on the codeword at the plurality of ECC protection levels by:

performing a first algebraic operation on the codeword using the first matrix and a second algebraic operation on the codeword using the second matrix;

performing a cubing operation on a result of the first algebraic operation;

inputting a result of the cubing operation into a first input of the multiplexer;

inputting a result of the second algebraic operation into a second input of the multiplexer; and

inputting an input indicating to perform the ECC operation at the plurality of ECC protection levels into a third input of the multiplexer.

15. The system of claim 14 , wherein the encoding unit operating circuit is configured to:

receive an input indicating which one of the plurality of ECC protection levels to generate the codeword for; and

generate the codeword for the one of the plurality of ECC protection levels responsive to receiving the input.

16. The system of claim 15 , wherein the host is configured to:

receive a selection of the one of the plurality of ECC protection levels to generate the codeword for from a user; and

send an indication of the selected one of the plurality of ECC protection levels to the memory device.

17. The system of claim 14 , wherein the operating circuit is configured to:

receive an input indicating which one of the plurality of ECC protection levels to perform the ECC operation at; and

perform the ECC operation at the one of the plurality of ECC protection levels responsive to receiving the input.

18. The system of claim 17 , wherein the operating circuit is configured to determine the one of the plurality of ECC protection levels to generate the codeword for based on a status of the memory cells of the array.

19. The system of claim 14 , wherein:

the operating circuit includes two additional matrices; and

the operating circuit is configured to:

generate the parity data of the codeword for a first one of the plurality of ECC protection levels using only one of the two additional matrices; and

generate the parity data of the codeword for a second one of the plurality of ECC protection levels using each of the two additional matrices.