FAST, ENERGY EFFICIENT 6T SRAM ARRAYS USING HARVESTED DATA
A transistor memory device includes transistor storage elements storing a capacitance at each transistor storage element. Each transistor storage element includes a word line port that selects a bitcell and a bitline. Each transistor storage element performs a read data access from or a write data access to each remaining transistor storage element to increase a SNM. The device includes a harvest node configured to store a harvested charge transferred from the bitline. The transistor memory device includes a capacitor divider between the bitline and the harvest node of a first transistor storage element and configured to maintain a voltage swing on the bitline. The device further includes a harvest circuit configured to, in response to the read data access performed by the first transistor storage element, decouple the harvest node from a ground and invert a voltage equal to a potential difference between the bitline and the harvest node.
1 . A 6 Transistor Memory device comprising:
a plurality of conventional 6 transistor storage elements each with a single Word Line port to select the cell and a pair of Bit Line ports to read data from or write data to the storage element
a harvest terminal that replaces the reference ground potential terminal of the conventional 6 transistor storage element
a harvest circuit coupled to the harvest terminal of a plurality of storage elements with the harvest circuit responsive to a Read access such that it inverts the voltage equal to the potential difference between the Bit Line terminal and the harvest terminal of the selected storage element among a plurality of storage elements that share these terminals