Automation methods for 3D integrated circuits and devices
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes logic and the second level includes memory; and then obtaining a first placement of at least portion of the second level, where the first placement includes placement of a first memory array, where the Circuit includes a plurality of connections between the first level and the second level; and performing a second placement, where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array, where the performing a second placement includes using a placer executed by a computer, where the placer is a part of a Computer Aided Design tool, and where the logic includes a first logic circuit configured to read data from the first memory array.
1. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level,
wherein said first level comprises logic and said second level comprises memory; and then
obtaining a first placement of at least portion of said second level,
wherein said first placement comprises a placement of a first memory array,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and
performing a second placement,
wherein performing said second placement comprises placing said first logic circuit based on said first placement of said first memory array,
wherein said performing a second placement comprises using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool, and
wherein said logic comprises a first logic circuit configured to read data from said first memory array.
2. The method according to claim 1 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said first routing layers.
3. The method according to claim 1 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.
4. The method according to claim 1 ,
wherein said second level comprises a plurality of memory arrays.
5. The method according to claim 1 , further comprising:
performing a third placement comprising placement of said plurality of connections.
6. A 3D Integrated Circuit made according to the method of claim 1 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.
7. The method according to claim 1 , further comprising:
performing a third placement comprising placement of said plurality of connections,
wherein said third placement is based on said first placement.
8. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level,
wherein said first level comprises logic and said second level comprises memory,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and then
obtaining a first placement of at least portion of said plurality of connections,
performing a second placement of said first level based on said first placement,
wherein said performing a second placement comprises using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool;
wherein said logic comprises a first logic circuit configured to read data from said first memory array.
9. The method according to claim 8 , further comprising;
performing a third placement of said second level based on said first placement,
wherein said third placement comprises a placement of a first memory array.
10. The method according to claim 8 ,
wherein said second level comprises a plurality of memory arrays.
11. The method according to claim 8 ,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said second routing layers.
12. A 3D Integrated Circuit made according to the method of claim 8 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.
13. The method according to claim 8 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said first routing layers.
14. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level,
wherein said first level comprises logic and said second level comprises memory; and then
obtaining a first placement of at least a portion of said second level,
wherein said first placement comprises a placement of a first memory array and a second memory array,
wherein said 3D Integrated Circuit comprises a plurality of connections between said first level and said second level; and
performing a second placement of said first level based on said first placement,
wherein said performing a second placement comprises using a placer executed by a computer,
wherein said placer is a part of a Computer Aided Design (CAD) tool,
wherein said logic comprises a first logic circuit configured to read data from said first memory array, and
wherein performing said second placement comprises placing said first logic circuit based on said first placement of said first memory array.
15. The method according to claim 14 ,
wherein said first level comprises first routing layers,
wherein said second level comprises second routing layers, and said method further comprises:
performing routing for said first routing layers.
16. The method according to claim 14 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.
17. The method according to claim 14 ,
wherein said second level comprises at least three independent memory arrays.
18. The method according to claim 14 , further comprising:
a third placement comprising placement of said plurality of connections.
19. A 3D Integrated Circuit made according to the method of claim 14 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form the integrated circuit.
20. The method according to claim 14 , further comprising:
a third placement comprising placement of said plurality of connections,
wherein said third placement is based on said first placement.