Configurable scan chain architecture for multi-port memory
Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.
1. A device comprising:
first datapath circuitry having input devices that receive data from a number of write ports and provide first data;
second datapath circuitry having logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal; and
third datapath circuitry having output devices that receive the first data from the logic gates and provide second data to a number of first read ports,
wherein:
the number of first read ports is greater than the number of write ports, and the device further comprises: one or more second read ports, wherein:
the one or more second read ports comprise an additional quantity of read ports in comparison to the write ports, and
the one or more second read ports are configured to capture a replication of at least a portion of the received second data during a scan capture or scan shift operation.
2. The device of claim 1 , wherein the device further comprises scan chain architecture with a memory design-for-test (DFT) design for multi-port memory applications.
3. The device of claim 1 , wherein:
the input devices have multiple latches per data bit;
the output devices have a single latch per data bit; and
the logic gates are coupled between the input devices and the output devices,
wherein the logic gates combine the first data from the multiple latches into single latched data provided to the output devices.
4. The device of claim 1 , wherein the number of input devices is greater than the number of output devices.
5. The device of claim 1 , wherein the input devices comprise two (2) latches per data bit, and wherein the output devices comprise one (1) latch per data bit.
6. The device of claim 1 , wherein the number of write ports is equal to or greater than two, and wherein the number of first read ports is equal to or greater than three, and wherein the number of first read ports is at least greater than the number of write ports.
7. The device of claim 1 , wherein:
the logic gates include multiple logic gates including a first logic gate and a second logic gate,
the first logic gate receives multiple first data from at least two (2) input latches of the input devices and then provides single first latched data to the second logic gate, and
the second logic gate receives the single first latched data from the first logic gate, receives the read bitline signal, and provides the single first latched data to an output latch based on a design-for-test (DFT) signal.
8. A device comprising:
first datapath circuitry having input latches that receive data from a number of write ports and provide first latched data;
second datapath circuitry having logic gates that receive the first latched data from the input latches and provide the first latched data based on a read bitline signal; and
third datapath circuitry having output latches that receive the first latched data from the logic gates and provide second latched data to a number of read ports, wherein:
the number of the write ports is greater than the number of the read ports, and
the received data, from one or more additional write ports, is configured to be captured by one or more of the read ports that receive the second latched data from the third datapath circuitry originating from at least two of the write ports during a scan capture or scan shift operation.
9. The device of claim 8 , wherein the device further comprises scan chain architecture with a memory design-for-test (DFT) design for multi-port memory applications.
10. The device of claim 8 , wherein:
the input latches have multiple latches per data bit;
the output latches have a single latch per data bit; and
the logic gates are coupled between the input latches and the output latches,
wherein the logic gates combine the first latched data from the multiple latches into single latched data provided to the output latches.
11. The device of claim 8 , wherein the number of input latches is greater than the number of output latches.
12. The device of claim 8 , wherein the input latches comprise two (2) latches per data bit, and wherein the output latches comprise one (1) latch per data bit.
13. The device of claim 8 , wherein the number of read ports is equal to or greater than two, and wherein the number of write ports is equal to or greater than three, and wherein the number of write ports is at least greater than the number of read ports.
14. The device of claim 8 , wherein:
the logic gates include multiple logic gates including a first logic gate and a second logic gate,
the first logic gate receives multiple first latched data from at least two (2) input latches of the input latches and then provides single first latched data to the second logic gate, and
the second logic gate receives the single first latched data from the first logic gate, receives the read bitline signal, and provides the single first latched data to the output latches based on a design-for-test (DFT) signal.
15. A device comprising:
first datapath circuitry having input latches that receive data from a number of write ports and provide first latched data;
second datapath circuitry having logic gates that receive the first latched data from the input latches and provide the first latched data based on a read bitline signal; and
third datapath circuitry having output latches that receive the first latched data from the logic gates and provide second latched data to a number of read ports,
wherein the number of output latches is greater than the number of input latches, and wherein the number of read ports is greater than the number of write ports.
16. The device of claim 15 , wherein the device further comprises scan chain architecture with a memory design-for-test (DFT) design for multi-port memory applications.
17. The device of claim 15 , wherein:
the input latches have a single input latch per data bit;
the output latches have a single output latch per data bit; and
the logic gates are coupled between the input latches and the output latches,
wherein the logic gates receive the first latched data from the single input latch and provide the first latched data to the single output latch based on the read bitline signal.
18. The device of claim 15 , wherein the input latches comprise two (2) latches per data bit, and wherein the output latches comprise one (1) latch per data bit.
19. The device of claim 15 , wherein the number of write ports is equal to or greater than two, and wherein the number of read ports is equal to or greater than three, and wherein the number of read ports is at least greater than the number of write ports.
20. The device of claim 15 , wherein the number of write ports is equal to or greater than three, and wherein the number of read ports is equal to or greater than four, and wherein the number of read ports is at least greater than the number of write ports.