IP Library › Granted Patent US 12,413,568
Granted Patent B2
US 12,413,568 · App. 17/955,421 · Granted Sep 9, 2025

Method and system for distributing keys

Inventors: Norman Vernon Douglas Stewart (Markham, CA); Mihir Shaileshbhai Doctor (Santa Clara, CA); Omar Fakhri Ahmed (Markham, CA); Hemaprabhu Jayanna (Santa Clara, CA); John Traver (Santa Clara, CA)
Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
H04L63/062H04W12/04
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,413,568
App. No.
17/955,421
Granted
Sep 9, 2025
Kind
B2
Abstract

A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.

Claims (40)

1. A method performed by a system on chip (SOC) for managing security keys, the method comprising:

detecting, via a private key distribution bus of the SoC, that a device is connected to a first component of the SoC;

in response to the detecting:

generating a key based on the device requiring the key and a security mode of the SoC, and

distributing, via the private key distribution bus of the SoC, the key to the first component; and

selectively destroying the key in response to changes associated with the security mode.

2. The method of claim 1 wherein upon the security mode being a first security mode in operation for communication, the key is generated and distributed to the first component.

3. The method of claim 1 wherein a key size is selected for generation based upon a type of the device.

4. The method of claim 2 , further comprising switching from the first security mode to a second security mode.

5. The method of claim 1 , wherein the key is selectively destroyed when the security mode changes from a secure mode to a non-secure mode.

6. The method of claim 1 , further comprising:

destroying the key when the device is disconnected.

7. The method of claim 6 , further comprising deleting an associated rule for the key generated for the first component.

8. The method of claim 1 wherein the first component includes one or more of a Peripheral Component Interconnect Express (PCIe) component, a video component, a display component or a unified memory controller component.

9. The method of claim 1 , wherein the device is a video graphics card or a network card.

10. The method of claim 1 , wherein the first component is a PCIe controller or PCIe network adapter.

11. A key distribution system, comprising:

a first module;

a private key distribution bus; and

a processor communicatively the first module via the private key distribution bus,

wherein the processor configured to:

detect, via the private key distribution bus, that a device connected to the first module,

in response to the device being detected:

generate a key based on the device requiring the key and a security mode of the processor, and

distribute, via the private key distribution bus, the key to the first module, and

selectively destroy the key in response to changes associated with the security mode.

12. The key distribution system of claim 11 wherein upon the security mode being a first security mode in operation for communication, the key is generated and distributed to the first module.

13. The key distribution system of claim 12 , further comprising the processor switching from the first security mode to a second security mode.

14. The key distribution system of claim 13 wherein the key is selectively destroyed when the security mode changes from a secure mode to a non-secure mode.

15. The key distribution system of claim 11 wherein a key size is selected for generation based upon a type of the device.

16. The key distribution system of claim 11 wherein the processor is further configured to destroy the key when the device is disconnected.

17. The key distribution system of claim 11 wherein the first module includes one or more of a Peripheral Component Interconnect Express (PCIe) component, a video component, a display component or a unified memory controller component.

18. The key distribution system of claim 11 , wherein the device is a video graphics card or a network card.

19. A non-transitory computer-readable medium for managing security keys, the non-transitory computer-readable medium having instructions recorded thereon that, when executed by a processor of a system on chip (SOC), cause the SoC to perform operations including:

detecting, via a private key distribution bus of the SoC, that a device is connected to a first component of the SoC;

in response to the detecting:

generating a key for the first component based on the device requiring the key and a security mode of the SoC, and

distributing, via the private key distribution bus of the SoC, the key to the first component; and

selectively destroying the key in response to changes associated with the security mode.

20. The non-transitory computer-readable medium of claim 19 , wherein the device is a video graphics card or a network card.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2023
From: DOCTOR, MIHIR SHAILESHBHAI; JAYANNA, HEMAPRABHU; TRAVER, JOHN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 062296/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2023
From: STEWART, NORMAN VERNON DOUGLAS; AHMED, OMAR FAKHRI
To: ATI TECHNOLOGIES ULC
Reel/Frame 062296/0379 →
Continuity (1)
Related Publication 20240106813A1 · Mar 28, 2024
References Cited (20)
US 11831655B2 · Lee · 2023 [cited by examiner]
US 20010038695A1 · Kim · 2001 [cited by examiner]
US 20060178131A1 · Huotari · 2006 [cited by examiner]
US 20090164663A1 · Ransom · 2009 [cited by examiner]
US 20110119489A1 · Garcia Morchon · 2011 [cited by examiner]
US 20120057697A1 · Holtmanns · 2012 [cited by examiner]
US 20120328103A1 · Feng · 2012 [cited by examiner]
US 20140165216A1 · Kwag · 2014 [cited by examiner]
US 20160239556A1 · Oh · 2016 [cited by examiner]
US 20160315762A1 · Moon et al. · 2016 [cited by applicant]
US 20170214717A1 · Bush · 2017 [cited by examiner]
US 20170255423A1 · Yoshida · 2017 [cited by examiner]
US 20180131511A1 · Taylor · 2018 [cited by examiner]
US 20180183581A1 · Elbaz et al. · 2018 [cited by applicant]
US 20190239033A1 · Douglas · 2019 [cited by examiner]
US 20200296099A1 · Shanbhogue et al. · 2020 [cited by applicant]
US 20200374130A1 · Strong et al. · 2020 [cited by applicant]
US 20210352110A1 · Huffman · 2021 [cited by examiner]
US 20220303763A1 · Guo · 2022 [cited by examiner]
KR 1020150131696A · 2015 [cited by applicant]