IP Library Granted Patent US 12,581,735
Granted Patent B2
US 12,581,735 · App. 17/955,813 · Granted Mar 17, 2026

Display device and manufacturing method of the same

Inventors: Jeong Su Park (Asan-si, KR); Jin Taek Kim (Yongin-si, KR); Hyun Kim (Seoul, KR); Sung Jin Lee (Yongin-si, KR); Jong Chan Lee (Suwon-si, KR); Woong Hee Jeong (Seoul, KR); Jung Eun Hong (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
H10D86/60H01L24/03H01L24/05H01L24/06H01L25/167H10D86/0231H10D86/441H10D86/451H10H20/831H01L2224/03019H01L2224/0362H01L2224/05018H01L2224/05022H01L2224/05082H01L2224/05083H01L2224/05124H01L2224/05138H01L2224/05144H01L2224/05147H01L2224/05155H01L2224/05166H01L2224/05171H01L2224/0518H01L2224/05553H01L2224/05558H01L2224/05566H01L2224/05573H01L2224/05624H01L2224/05686H01L2224/0603H01L2924/0106H01L2924/0549H10H20/032
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Quick Facts
Patent No.
US 12,581,735
App. No.
17/955,813
Granted
Mar 17, 2026
Kind
B2
Abstract

A display device includes a substrate including a display area and a pad area; a first conductive layer including a first pad electrode in the pad area; and a second conductive layer the second conductive layer includes a second pad electrode on the first pad electrode in the pad area; the first pad electrode and the second pad electrode overlap in a first direction that is a thickness direction, and do not overlap in a second direction perpendicular to the first direction.

Claims (61)

1 . A display device comprising:

a substrate including a display area and a pad area;

a first conductive layer disposed on the substrate, the first conductive layer comprising a first signal line disposed in the display area and a first pad electrode disposed in the pad area;

a buffer layer disposed on the first conductive layer;

a semiconductor layer disposed on the buffer layer in the display area;

a gate insulating layer disposed on the semiconductor layer;

a second conductive layer disposed on the gate insulating layer, wherein the second conductive layer comprises:

a gate electrode overlapping the semiconductor layer in the display area;

a first electrode overlapping on a side of the semiconductor layer in the display area and electrically connected to the first signal line through a contact hole penetrating the buffer layer and the gate insulating layer;

a second electrode disposed on another side of the semiconductor layer in the display area; and

a second pad electrode disposed on the first pad electrode in the pad area, and

the first pad electrode and the second pad electrode overlap in a first direction that is a thickness direction, and do not overlap in a second direction perpendicular to the first direction.

2 . The display device of claim 1 , wherein a width of the first pad electrode in the second direction is substantially the same as a width of the second pad electrode in the second direction.

3 . The display device of claim 2 , wherein an area of the first pad electrode and an area of the second pad electrode are substantially the same in a plan view.

4 . The display device of claim 1 , wherein a width of the first pad electrode in the second direction is greater than a width of the second pad electrode in the second direction.

5 . The display device of claim 4 , wherein an area of the first pad electrode is larger than an area of the second pad electrode in a plan view.

6 . The display device of claim 4 , wherein

the semiconductor layer, the gate electrode, the first electrode, and the second electrode form a transistor,

the first pad electrode and the second pad electrode form pads,

the display device comprises a driver applying a data signal and a scan signal to the transistor, and

the pads comprise a data pad receiving the data signal from the driver and a scan pad receiving the scan signal from the driver.

7 . The display device of claim 6 , wherein

the first conductive layer comprises a data line transmitting the data signal from the data pad and a scan line transmitting the scan signal from the scan pad,

data pads of the pads being spaced apart from each other,

scan pads of the pads being spaced apart from each other, and

the scan line extends across a space between the data pads.

8 . The display device of claim 7 , wherein the scan line and the first pad electrode of the data pad are spaced apart from each other.

9 . The display device of claim 7 , wherein

the first conductive layer comprises a data check line extending from the first pad electrode of the data pad, and

the data check line extends across a space between the scan pads.

10 . The display device of claim 9 , wherein the data check line and the first pad electrode of the scan pad are spaced apart from each other.

11 . The display device of claim 1 , wherein

the buffer layer is disposed between the first pad electrode and the second pad electrode in the pad area, and

the first pad electrode and the second pad electrode are electrically connected through a pad contact hole penetrating the buffer layer.

12 . The display device of claim 11 , further comprising:

a via insulating layer disposed on the second conductive layer in the display area;

an electrode disposed on the via insulating layer in the display area;

a first insulating layer disposed on the electrode; and

a light emitting element disposed on the first insulating layer in the display area.

13 . The display device of claim 12 , further comprising:

a connection electrode layer disposed on the light emitting element, the connection electrode layer comprising:

a connection electrode electrically connected to the light emitting element in the display area; and

a third pad electrode disposed on the second pad electrode in the pad area.

14 . The display device of claim 13 , wherein the third pad electrode is electrically connected to the second pad electrode.

15 . The display device of claim 11 , wherein the pad contact hole is provided in plural.

16 . A manufacturing method of a display device, comprising:

preparing a substrate including a display area and a pad area;

forming a first conductive layer disposed on the substrate, the first conductive layer comprising a first signal line disposed in the display area and a first pad electrode disposed in the pad area;

forming a buffer layer disposed on the first conductive layer;

forming a semiconductor layer disposed on the buffer layer in the display area;

forming a gate insulating layer disposed on the semiconductor layer; and

forming a second conductive layer disposed on the gate insulating layer, wherein the second conductive layer comprises:

a gate electrode overlapping the semiconductor layer in the display area;

a first electrode overlapping a side of the semiconductor layer in the display area and electrically connected to the first signal line through a contact hole penetrating the buffer layer and the gate insulating layer;

a second electrode disposed on another side of the semiconductor layer in the display area; and

a second pad electrode disposed on the first pad electrode in the pad area, and

the first pad electrode and the second pad electrode overlap in a first direction that is a thickness direction, and do not overlap in a second direction perpendicular to the first direction.

17 . The manufacturing method of claim 16 , wherein a width of the first pad electrode in the second direction is substantially the same as a width of the second pad electrode in the second direction.

18 . The manufacturing method of claim 17 , wherein an area of the first pad electrode and an area of the second pad electrode are substantially the same in a plan view.

19 . The manufacturing method of claim 16 , wherein a width of the first pad electrode in the second direction is greater than a width of the second pad electrode in the second direction.

20 . The manufacturing method of claim 19 , wherein an area of the first pad electrode is larger than an area of the second pad electrode in a plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2022
From: PARK, JEONG SU; KIM, JIN TAEK; KIM, HYUN; LEE, SUNG JIN; LEE, JONG CHAN; JEONG, WOONG HEE; HONG, JUNG EUN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 061569/0555 →
Priority Claims (1)
KR 10-2022-0015297 · Feb 7, 2022 · national
Continuity (1)
Related Publication 20230253412A1 · Aug 10, 2023
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