Operation method of memory device and operation method of memory system including the same

1. An operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate, the method comprising:

performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter; and

after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter,

wherein n is an integer greater than 1 and k is an integer greater than or equal to n, and

wherein the first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

2. The method of claim 1 , further comprising:

after the k-th program loop is performed, performing (k+1)-th to m-th program loops based on the first program parameter,

wherein m is an integer greater than k.

3. The method of claim 1 , wherein a subset of the memory cells of the selected memory cells form a threshold voltage distribution corresponding to a specific program state through the n-th to k-th program loops.

4. The method of claim 3 , wherein, in each of the n-th to k-th program loops, the subset of the memory cells of the selected memory cells are verified by using a verify voltage for verifying the specific program state.

5. The method of claim 1 , wherein a second program voltage increment belonging to the second program parameter used in the n-th to k-th program loops is smaller than a first program voltage increment belonging to the first program parameter used in the first to (n−1)-th program loops.

6. The method of claim 5 , wherein a second bit line forcing voltage belonging to the second program parameter used in the n-th to k-th program loops is smaller than a first bit line forcing voltage belonging to the first program parameter used in the first to (n−1)-th program loops.

7. The method of claim 6 , wherein a decreasing ratio of the second program voltage increment to the first program voltage increment is equal to a decreasing ratio of the second bit line forcing voltage to the first bit line forcing voltage.

8. The method of claim 5 , wherein a second 2-step verify range belonging to the second program parameter used in the n-th to k-th program loops is greater than a first 2-step verify range belonging to the first program parameter used in the first to (n−1)-th program loops.

9. The method of claim 1 , further comprising:

after the n-th program loop is performed, performing a cell counting operation on the selected memory cells connected to the selected word line from among the plurality of memory cells.

10. The method of claim 9 , wherein a result of the cell counting operation indicates the number of memory cells each having a threshold voltage between a first reference voltage and a second reference voltage from among the selected memory cells, and

wherein, when the result of the cell counting operation is greater than or equal to a reference value, the n-th program loop is performed based on the second program parameter.

11. The method of claim 1 , wherein the n-th to k-th program loops are set by an external memory controller.

12. A program method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate, the method comprising:

performing a first program step on selected memory cells connected to a selected word line from among the plurality of memory cells by applying a first program voltage to the selected word line;

performing a first verify step on the selected memory cells by applying a first verify voltage set to the selected word line;

performing a second program step on the selected memory cells by applying a second program voltage to the selected word line and applying a program-inhibit voltage, a ground voltage, and a first bit line forcing voltage to bit lines corresponding to the selected memory cells, based on a result of the first verify step;

performing a second verify step on the selected memory cells by applying a second verify voltage set to the selected word line; and

performing a third program step on the selected memory cells by applying a third program voltage to the selected word line and applying the program-inhibit voltage, the ground voltage, and a second bit line forcing voltage to the bit lines corresponding to the selected memory cells, based on a result of the second verify step,

wherein a difference between the first and second program voltages is a first program voltage increment, a difference between the second and third program voltages is a second program voltage increment different from the first program voltage increment, and the first bit line forcing voltage is different from the second bit line forcing voltage.

13. The method of claim 12 , wherein the second program voltage increment is smaller than the first program voltage increment, and the second bit line forcing voltage is smaller than the first bit line forcing voltage.

14. The method of claim 13 , wherein a decreasing ratio of the second program voltage increment to the first program voltage increment is equal to a decreasing ratio of the second bit line forcing voltage to the first bit line forcing voltage.

15. The method of claim 12 , wherein the first verify step is performed based on a first 2-step verify range, and the second verify step is performed based on a second 2-step verify range greater than the first 2-step verify range.

16. An operation method of a memory system which includes a memory device and a memory controller configured to control the memory device, the method comprising:

sending, by the memory controller, a program command to the memory device; and

performing, by the memory device, a program operation in response to the program command,

wherein the program operation includes:

performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among a plurality of memory cells included in the memory device, based on a first program parameter; and

after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter,

wherein n is an integer greater than 1 and k is an integer greater than or equal to n, and

wherein the first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

17. The method of claim 16 , further comprising:

managing, by the memory controller, program/erase cycles of the memory device; and

controlling, by the memory controller, the first and second program parameters based on the program/erase cycles.

18. The method of claim 16 , further comprising:

sending, by the memory controller, a suspend command to the memory device while the memory device performs the program operation;

suspending, by the memory device, the program operation being performed;

sending, by the memory controller, a resume command to the memory device; and

resuming, by the memory device, the suspended program operation.

19. The method of claim 18 , wherein the memory device changes the first program parameter into a third program parameter and changes the second program parameter into a fourth program parameter, and

wherein the memory device resumes the suspended program operation based on the third program parameter and the fourth program parameter.

20. The method of claim 16 , wherein memory cells corresponding to a specific program state from among the selected memory cells are programmed through the n-th to k-th program loops, and

wherein the specific program state is determined by the memory controller.