Double stitch wirebonds
In some examples, a semiconductor package comprises an electrically conductive surface and a bond wire coupled to the electrically conductive surface. The bond wire includes a first stitch bond coupled to the electrically conductive surface, and a second stitch bond contiguous with the first stitch bond and coupled to the electrically conductive surface. The second stitch bond is partially, but not completely, overlapping with the first stitch bond.
1 . A semiconductor package, comprising:
an electrically conductive surface; and
a bond wire coupled to the electrically conductive surface, the bond wire including:
a first stitch bond coupled to the electrically conductive surface; and
a second stitch bond contiguous with the first stitch bond and coupled to the electrically conductive surface, the second stitch bond partially, but not completely, overlapping with the first stitch bond, wherein:
a top surface of the bond wire includes a first ridge and a second ridge;
a plane along the top surface of the first ridge is above a plane along a top surface of the second ridge.
2 . The semiconductor package of claim 1 , wherein the top surface of the bond wire includes a depression between the first and second ridges.
3 . The semiconductor package of claim 2 , wherein the top surface includes a depression on multiple sides of the first ridge.
4 . The semiconductor package of claim 1 , wherein a length over which the first stitch bond is coupled to the electrically conductive surface ranges from 100% to 150% of a diameter of the bond wire.
5 . The semiconductor package of claim 1 , wherein a length over which the second stitch bond is coupled to the electrically conductive surface ranges from 100% to 150% of a diameter of the bond wire.
6 . A semiconductor package, comprising:
an electrically conductive surface; and
a bond wire coupled to the electrically conductive surface, the bond wire including:
a first stitch bond between the bond wire and the electrically conductive surface, the first stitch bond vertically coinciding with a first depression on a top surface of the bond wire; and
a second stitch bond between the bond wire and the electrically conductive surface, the second stitch bond vertically coinciding with a second depression on the top surface of the bond wire,
wherein:
a first end of the first stitch bond overlaps with a second end of the second stitch bond;
a ridge is positioned between the first depression and the second depression; and
a plane along the top surface of the first ridge is below a plane along a highest point of the top surface of the bond wire that is in contact with the electrically conductive surface.
7 . The semiconductor package of claim 6 , wherein a distal end of the second stitch bond includes a tail bond that is vertically aligned with a second ridge on the top surface of the bond wire.
8 . The semiconductor package of claim 6 , wherein a length over which the first stitch bond is coupled to the electrically conductive surface ranges from 100% to 150% of a diameter of the bond wire.
9 . The semiconductor package of claim 6 , wherein a length over which the second stitch bond is coupled to the electrically conductive surface ranges from 100% to 150% of a diameter of the bond wire.
10 . A semiconductor package, comprising:
a surface of a lead; and
a bond wire coupled to the lead, the bond wire including:
a first stitch bond contacting the surface; and
a second stitch bond contiguous with the first stitch bond and contacting surface, the second stitch bond partially, but not completely, overlapping with the first stitch bond, wherein:
a top surface of the bond wire includes a first ridge and a second ridge;
a first plane along the top surface of the first ridge is above a second plane along a top surface of the second ridge; and
a plane along a highest point of the top surface of the bond wire that is in contact with the lead is above the first plane.
11 . The semiconductor package of claim 10 , wherein the package further includes a semiconductor die including a bond pad.
12 . The semiconductor package of claim 11 , wherein a portion of the bond wire is attached to the bond pad.
13 . The semiconductor package of claim 12 , wherein the portion of the bond wire is attached to the bond pad via a ball bond.
14 . The semiconductor package of claim 10 , wherein a distal end of the second stitch bond includes a tail bond that is vertically aligned with a second ridge on the top surface of the bond wire.
15 . The semiconductor package of claim 10 , wherein the second stich bond is created by moving a capillary horizontally away from the first stitch bond by a distance of at least two times a diameter of the bond wire.