Display apparatus
A display apparatus a substrate including a lower organic layer, a lower barrier layer, an upper organic layer, and an upper barrier layer, which are sequentially stacked on each other, a pixel circuit layer on the substrate, and a display element layer on the pixel circuit layer. The upper barrier layer includes a first inorganic barrier layer on the upper organic layer, a shielding layer on the first inorganic barrier layer, the shielding layer comprising an oxide semiconductor material, and a second inorganic barrier layer on the shielding layer.
1 . A display apparatus comprising:
a substrate including a lower organic layer, a lower barrier layer, an upper organic layer, and an upper barrier layer, which are sequentially stacked on each other;
a pixel circuit layer on the substrate; and
a display element layer on the pixel circuit layer,
wherein the upper barrier layer includes:
a first inorganic barrier layer on the upper organic layer;
a shielding layer on the first inorganic barrier layer, the shielding layer including an oxide semiconductor material; and
a second inorganic barrier layer on the shielding layer.
2 . The display apparatus of claim 1 , wherein the shielding layer includes at least one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and indium tin gallium zinc oxide (ITGZO).
3 . The display apparatus of claim 1 , wherein a thickness of the shielding layer is about 50 Å to about 10,000 Å.
4 . The display apparatus of claim 1 , wherein the shielding layer covers an entire surface of the substrate.
5 . The display apparatus of claim 1 , wherein the upper organic layer includes polyimide.
6 . The display apparatus of claim 1 , further comprising:
a first buffer layer and a second buffer layer that are between the substrate and the pixel circuit layer, wherein;
the second inorganic barrier layer includes a first inorganic insulating material,
the first buffer layer includes a second inorganic insulating material, and
the first inorganic insulating material is different from the second inorganic insulating material.
7 . The display apparatus of claim 6 , wherein the second inorganic insulating material includes silicon nitride (SiN x ).
8 . The display apparatus of claim 7 , wherein the first inorganic insulating material includes silicon oxide (SiO x ).
9 . The display apparatus of claim 6 , wherein the first inorganic barrier layer includes the first inorganic insulating material.
10 . The display apparatus of claim 6 , wherein a sum of a thickness of the second inorganic barrier layer, a thickness of the first buffer layer, and a thickness of the second buffer layer is about 3,500 Å to about 15,000 Å.
11 . The display apparatus of claim 1 , wherein:
the pixel circuit layer includes a thin-film transistor;
the thin-film transistor includes:
a semiconductor layer;
a gate electrode at least partially overlapping the semiconductor layer in a plan view; and
an electrode layer on the gate electrode, and
the shielding layer and the semiconductor layer include a same material.
12 . An electronic device comprising the display apparatus of claim 1 .
13 . A method of manufacturing a display apparatus, the method comprising:
forming a lower organic layer on a carrier substrate;
forming a lower barrier layer on the lower organic layer;
forming an upper organic layer on the lower barrier layer;
forming an upper barrier layer on the upper organic layer, the upper barrier layer including an oxide semiconductor material;
forming a pixel circuit layer on the upper barrier layer;
forming a display element layer on the pixel circuit layer; and
removing the carrier substrate.
14 . The method of claim 13 , wherein the forming of the upper barrier layer comprises:
forming a first inorganic barrier layer on the upper organic layer;
forming a shielding layer on the first inorganic barrier layer, the shielding layer including an oxide semiconductor material; and
forming a second inorganic barrier layer on the shielding layer.
15 . The method of claim 14 , wherein the shielding layer includes at least one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and indium tin gallium zinc oxide (ITGZO).
16 . The method of claim 14 , wherein a thickness of the shielding layer is about 50 Å to about 10,000 Å.
17 . The method of claim 14 , wherein, a proportion of oxygen in a mixed gas inside a chamber is about 10% to about 80% in the forming of the shielding layer.
18 . The method of claim 14 , wherein:
the forming of the pixel circuit layer comprises:
sequentially forming a first buffer layer and a second buffer layer on the upper barrier layer;
forming a semiconductor layer on the second buffer layer;
forming a gate electrode on the semiconductor layer; and
forming an electrode layer on the gate electrode, and
the semiconductor layer and the shielding layer include a same material.
19 . The method of claim 18 , wherein:
the second inorganic barrier layer includes a first inorganic insulating material,
the first buffer layer includes a second inorganic insulating material, and
the first inorganic insulating material is different from the second inorganic insulating material.
20 . The method of claim 19 , wherein the second inorganic insulating material includes silicon nitride (SiN x ).
21 . The method of claim 18 , wherein a sum of a thickness of the second inorganic barrier layer, a thickness of the first buffer layer, and a thickness of the second buffer layer is about 3,500 Å to about 15,000 Å.