IP Library › Granted Patent US 12,148,498
Granted Patent B2
US 12,148,498 · App. 17/959,191 · Granted Nov 19, 2024

Post package repair management

Inventors: Danilo Caraccio (Milan, IT); Antonino Caprì (Bergamo, BG); Daniele Balluchi (Cernusco Sul Naviglio, IT); Massimiliano Patriarca (Milan, IT)
Assignee: Micron Technology, Inc.
G11C29/52G11C11/40615G11C11/4093
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Quick Facts
Patent No.
US 12,148,498
App. No.
17/959,191
Granted
Nov 19, 2024
Kind
B2
Abstract

A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

Claims (54)

1. A method, comprising:

detecting a soft post package repair (sPPR) request;

writing data stored in a target row of a memory array associated with the sPPR request to a buffer;

suspending execution of non-maintenance requests on the target row;

responsive to suspension of execution of non-maintenance requests on the target row, executing the sPPR request on the target row; and

subsequent to completion of the sPPR request:

resuming execution of non-maintenance requests on the target row; and

writing the data stored in the buffer to the repaired target row.

2. The method of claim 1 , wherein writing the data of the target row to the buffer comprises setting a retain flag associated with the target row.

3. The method of claim 2 , wherein writing the repaired data comprises unsetting the retain flag.

4. The method of claim 1 , wherein writing the data of the target row to the buffer comprises:

performing a first write operation to write a first portion of the data of the target row to the buffer; and

performing a second write operation to write a second portion of the data of the target row to the buffer.

5. The method of claim 1 , wherein suspending execution of requests associated with the target row comprises queueing requests associated with the target row while the target row is being repaired.

6. The method of claim 1 , further comprising executing a non-maintenance request on data stored in the buffer concurrent with executing the sPPR request on the target row.

7. The method of claim 1 , wherein suspending execution of non-maintenance requests on the target row and executing the sPPR request on the target row occur concurrently.

8. The method of claim 1 , further comprising, subsequent to completion of the sPPR request, resetting a refresh counter of a controller coupled to the memory array.

9. A method, comprising:

detecting a hard post package repair (hPPR) request, wherein the hPPR request is associated with a target row of a memory array;

setting PPR parameters of a local controller of the memory array, wherein the PPR parameters indicate the target row;

executing the hPPR request on the target row to remap an address corresponding to the target row to a different row of the memory array; and

subsequent to completion of the hPPR request, resetting a refresh counter of the local controller.

10. The method of claim 9 , further comprising subsequent to completion of the hPPR request, executing, by the local controller, requests associated with the remapped target row.

11. An apparatus, comprising:

a control circuitry comprising a buffer, wherein the control circuitry is configured to:

suspend execution of requests associated with a target address associated with a memory device and a post package repair (PPR) request;

write data at a target address to the buffer; and

execute the PPR request on a row of the memory device corresponding to the target address.

12. The apparatus of claim 11 , wherein the control circuitry is further configured to write the data stored by the buffer to the memory device at the target address.

13. The apparatus of claim 11 , wherein the control circuitry is further configured to, subsequent to completion of the PPR request, resume execution of requests associated with the target address.

14. The apparatus of claim 11 , further comprising the memory device, wherein the control circuitry comprises a memory controller of a memory module comprising the memory device.

15. The apparatus of claim 11 , further comprising the memory device, wherein the control circuitry comprises a local controller resident on the memory device.

16. The apparatus of claim 11 , wherein the control circuitry is further configured to receive the PPR request from a host.

17. The apparatus of claim 11 , wherein the control circuitry is further configured to receive the PPR request from the memory device.

18. An apparatus, comprising:

a memory device; and

a local controller resident on the memory device, wherein the local controller is configured to:

execute a post package repair (PPR) request on a first row of the memory device corresponding to a target address associated with the memory device;

as part of execution of the PPR request, remap the target address to a second row of the memory device; and

subsequent to completion of the PPR request, reset a refresh counter of the local controller.

19. A non-transitory medium storing instructions executable by a processing device to:

detect a post package repair (PPR) request associated with a target row address associated with a memory device;

execute the PPR request on a row of the memory device to which the target row address corresponds;

responsive to the PPR request being a soft PPR (sPPR) request:

write data at the target row address to a buffer;

execute the sPPR request at the target row address; and

responsive to completion of the sPPR request, write the data stored in the buffer to the memory device at the target row address;

responsive to the PPR request being a hard PPR (hPPR) request:

execute the hPPR request at the target row address; and

responsive to completion of the hPPR request, reset a refresh counter associated with the memory device; and

subsequent to completion of the PPR request, resume execution of requests associated with the target row address.

20. The medium of claim 19 , further storing instructions executable to:

concurrent with execution of the sPPR request, set a retain flag associated with the target row address; and

responsive to completion of the sPPR request, unset the retain flag.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2022
From: CARACCIO, DANILO; BALLUCHI, DANIELE; CAPRI, ANTONINO; PATRIARCA, MASSIMILIANO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 061294/0137 →
Continuity (2)
Provisional Application 63348424 · Jun 2, 2022
Related Publication 20230395184A1 · Dec 7, 2023