IP Library Granted Patent US 11,906,862
Granted Patent B2
US 11,906,862 · App. 17/959,306 · Granted Feb 20, 2024

Display device and semiconductor device

Inventors: Isao Suzumura (Tokyo, JP); Fumiya Kimura (Tokyo, JP); Kazuhide Mochizuki (Tokyo, JP); Hitoshi Tanaka (Tokyo, JP); Kenichi Akutsu (Tokyo, JP); Atsuko Shimada (Tokyo, JP)
Assignee: JAPAN DISPLAY INC.
G02F1/136286G02F1/1368G02F1/136227G02F1/13685G02F1/134318G02F1/134363G02F1/136295G02F2201/123G02F2201/40H01L27/1225
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,906,862
App. No.
17/959,306
Filed
Oct 4, 2022
Granted
Feb 20, 2024
Kind
B2
Art Unit
2871
USPC
349/47
Abstract

According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.

Claims (69)

1. A display device comprising:

a semiconductor layer including a first region, a second region and a channel region between the first region and the second region;

a first insulating layer located on the semiconductor layer;

a gate electrode located on the first insulating layer and opposing the channel region;

a second insulating layer located on the first insulating layer and the gate electrode;

a third insulating layer located on the second insulating layer;

a fourth insulating layer located on the third insulating layer;

an alignment film covering the fourth insulating layer;

a plurality of transparent conductive layers located between the second insulating layer and the alignment film;

a plurality of gate lines extending in a first direction and arranged in a second direction intersecting the first direction, with intervals therebetween; and

a plurality of source lines extending in the second direction and arranged in the first direction with intervals therebetween, to intersect the plurality of gate lines,

the plurality of transparent conductive layers including a pixel electrode between the fourth insulating layer and the alignment film, a first conductive layer between the second insulating layer and the third insulating layer, and a second conductive layer between the third insulating layer and the fourth insulating layer,

the first conductive layer being in contact with the second region of the semiconductor layer through a first contact hole formed in the first insulating layer and the second insulating layer,

the second conductive layer being in contact with the first conductive layer through a second contact hole formed in the third insulating layer,

the pixel electrode being in contact with the second conductive layer through a third contact hole formed in the fourth insulating layer,

the fourth insulating layer being in contact with the second conductive layer inside of the second contact hole,

the gate electrode being electrically connected to one of the plurality of gate lines and being located in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap,

the first region being electrically connected to one of the plurality of source lines,

the first conductive layer being located in an open area surrounded by a respective adjacent pair of gate lines of the plurality of gate lines and a respective adjacent pair of source lines of the plurality of source lines,

a width of the open area in the second direction is being less than a width of the gate line in the second direction.

2. The display device of claim 1 , wherein

the second region is located in the open area together with the first conductive layer, and

the semiconductor layer is formed of an oxide semiconductors.

3. The display device of claim 2 , further comprising:

a fifth insulating layer located on the fourth insulating layer; and

a sixth insulating layer located on the fifth insulating layer,

wherein

the plurality of transparent conductive layers further include a third conductive layer, a fourth conductive layer and a fifth conductive layer,

the third conductive layer is provided on the fourth insulating layer and covered by the fifth insulating layer, and opposes the second conductive layer,

the fourth conductive layer is provided on the fifth insulating layer, covered by the sixth insulating layer and electrically connected to the second conductive layer, and opposes the third conductive layer,

the fifth conductive layer is provided on the sixth insulating layer and electrically connected to the third conductive layer, and opposes the fourth conductive layer,

the pixel electrode is configured by the fourth conductive layer, and

the first conductive layer, the second conductive layer and the fourth conductive layer constitute a first electric system, which is electrically independent from a second electric system constituted by the third conductive layer and the fifth conductive layer.

4. A display device comprising:

a semiconductor layer including a first region, a second region and a channel region between the first region and the second region;

a first insulating layer located on the semiconductor layer;

a gate electrode located on the first insulating layer and opposing the channel region;

a second insulating layer located on the first insulating layer and the gate electrode;

a third insulating layer located on the second insulating layer;

a fourth insulating layer located on the third insulating layer;

an alignment film covering the fourth insulating layer;

a plurality of transparent conductive layers located between the second insulating layer and the alignment film;

a first substrate;

a second substrate disposed to oppose the first substrate with a gap therebetween; and

a liquid crystal layer held between the first substrate and the second substrate,

the plurality of transparent conductive layers including a pixel electrode between the fourth insulating layer and the alignment film, a first conductive layer between the second insulating layer and the third insulating layer, and a second conductive layer between the third insulating layer and the fourth insulating layer,

the first conductive layer being in contact with the second region of the semiconductor layer through a first contact hole formed in the first insulating layer and the second insulating layer,

the second conductive layer being in contact with the first conductive layer through a second contact hole formed in the third insulating layer,

the pixel electrode being in contact with the second conductive layer through a third contact hole formed in the fourth insulating layer,

the fourth insulating layer being in contact with the second conductive layer inside of the second contact hole,

the first substrate including the semiconductor layer, the first to fourth insulating layers, the alignment film, the gate electrode, and the plurality of transparent conductive layers, and a fifth insulating layer provided between the pixel electrode and the fourth insulating layer,

the third contact hole being formed in the fourth insulating layer and the fifth insulating layer,

the plurality of transparent conductive layers further including a third conductive layer provided between the fourth insulating layer and the fifth insulating layer,

the third conductive layer facing each of the pixel electrode and the second conductive layer,

the third conductive layer having an opening,

the opening of the third conductive layer overlapping the third contact hole.

5. The display device of claim 4 , wherein

the fifth insulating layer is in contact with the fourth insulating layer inside of the second contact hole.

6. The display device of claim 4 , wherein

the first substrate further includes a sixth insulating layer is provided on the pixel electrode and the fifth insulating layer,

the plurality of transparent conductive layers further includes a fifth conductive layer provided between the sixth insulating layer and the alignment film,

the alignment film is in contact with the fifth conductive layer and the sixth insulating layer, and

the pixel electrode faces each of the third conductive layer and the fifth conductive layer.

7. The display device of claim 6 , wherein

the plurality of transparent conductive layers further includes a fourth conductive layer provided between the fifth insulating layer and the sixth insulating layer,

the fourth conductive includes a connecting electrode and the pixel electrode,

the third conductive layer is in contact with the connecting electrode thorough a fourth contact hole formed in the fifth insulating layer,

the fifth conductive layer is in contact with the connecting electrode through a fifth contact hole formed in the sixth insulating layer, and

each of the third conductive layer and the fifth conductive layer is common electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
Priority Claims (1)
JP 2019-187855 · Oct 11, 2019 · national
Continuity (2)
Continuation 17066493 · Oct 9, 2020
Related Publication 20230026937A1 · Jan 26, 2023