Techniques for reducing DRAM power usage in performing read and write operations
Various embodiments include a memory device that is capable of performing memory access operations with reduced power consumption relative to prior approaches. The memory device receives early indication as to whether a forthcoming memory access operation is a read operation or a write operation. The memory device enables various circuits and disables other circuits depending on whether this early indication identifies an upcoming memory access operation as a read operation or a write operation. As a result, circuits that are not needed for an upcoming memory access operation are disabled earlier during the memory access operation relative to prior approaches. Disabling such circuits earlier during the memory access operation reduces power consumption without reducing memory device performance.
1. A computer-implemented method for performing a memory access operation on a memory device, the method comprising:
prior to receiving the memory access operation, receiving an indicator that identifies the memory access operation as including at least one of a read operation or a write operation;
enabling a first circuit based on the indicator; and
maintaining a disabled state of a second circuit based on the indicator.
2. The computer-implemented method of claim 1 , wherein:
the indicator identifies the memory access operation as including a read operation,
the first circuit includes at least one of a read clock distribution system, a read input/output circuit, or other read related circuitry, and
the second circuit includes at least one of a write clock distribution system, a write input/output circuit, or other write related circuitry.
3. The computer-implemented method of claim 1 , wherein:
the indicator identifies the memory access operation as including a write operation,
the first circuit includes at least one of a write clock distribution system, a write input/output circuit, or other write related circuitry, and
the second circuit includes at least one of a read clock distribution system, a read input/output circuit, or other read related circuitry.
4. The computer-implemented method of claim 1 , wherein:
the indicator identifies the memory access operation as included in a plurality of memory access operations including a read operation and a write operation,
the first circuit includes at least one of a read clock distribution system, a read input/output circuit, or other read related circuitry, and
the first circuit further includes at least one of a write clock distribution system, a write input/output circuit, or other write related circuitry.
5. The computer-implemented method of claim 1 , wherein the indicator is included in an activate command that initiates the memory access operation.
6. The computer-implemented method of claim 1 , wherein the indicator is included in a power command that identifies circuits within the memory device to enable or disable for power consumption management.
7. The computer-implemented method of claim 1 , further comprising, prior to receiving the memory access operation, receiving data that identifies at least one of a first clock distribution system or a first input/output circuit included in the first circuit.
8. The computer-implemented method of claim 7 , wherein the data further identifies at least one of a second clock distribution system or a second input/output circuit included in the second circuit.
9. The computer-implemented method of claim 1 , further comprising:
prior to receive the indicator, receiving a command to exit a power-down state; and
in response, exiting the power-down state.
10. The computer-implemented method of claim 1 , further comprising:
receiving a configuration command; and
configuring the memory device to utilize the indicator or ignore the indicator based on the configuration command.
11. A system, comprising:
a memory controller; and
a memory device coupled to the memory controller, and that:
prior to receiving a memory access operation, receives an indicator that identifies the memory access operation as including at least one of a read operation or a write operation;
enables a first circuit based on the indicator; and
maintains disabled state of a second circuit based on the indicator.
12. The system of claim 11 , wherein:
the indicator identifies the memory access operation as including a read operation,
the first circuit includes at least one of a read clock distribution system, a read input/output circuit, or other read related circuitry, and
the second circuit includes at least one of a write clock distribution system, a write input/output circuit, or other write related circuitry.
13. The system of claim 11 , wherein:
the indicator identifies the memory access operation as including a write operation,
the first circuit includes at least one of a write clock distribution system, a write input/output circuit, or other write related circuitry, and
the second circuit includes at least one of a read clock distribution system, a read input/output circuit, or other read related circuitry.
14. The system of claim 11 , wherein:
the indicator identifies the memory access operation as included in a plurality of memory access operations including a read operation and a write operation,
the first circuit includes at least one of a read clock distribution system, a read input/output circuit, or other read related circuitry, and
the first circuit further includes at least one of a write clock distribution system, a write input/output circuit, or other write related circuitry.
15. The system of claim 11 , wherein the indicator is included in an activate command that initiates the memory access operation.
16. The system of claim 11 , wherein the indicator is included in a power command that identifies circuits within the memory device to enable or disable for power consumption management.
17. The system of claim 11 , wherein the memory device further, prior to receiving the memory access operation, receives data that identifies at least one of a first clock distribution system or a first input/output circuit included in the first circuit.
18. The system of claim 17 , wherein the data further identifies at least one of a second clock distribution system or a second input/output circuit included in the second circuit.
19. The system of claim 11 , wherein the memory device further:
prior to receive the indicator, receives a command to exit a power-down state; and
in response, exits the power-down state.
20. The system of claim 11 , wherein the memory device further:
receives a configuration command; and
configures the memory device to utilize the indicator or ignore the indicator based on the configuration command.