Compute optimizations for low precision machine learning operations
One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.
1. A multi-chip module accelerator usable to execute tensor data processing instructions, the multi-chip module accelerator comprising:
a multi-chip module comprising:
an interconnect to a host processor;
a plurality of distinct chips integrated on the multi-chip module;
a memory stack including multiple memory dies; and
parallel processor circuitry communicatively coupled to the memory stack, the parallel processor circuitry comprising a plurality of multiprocessor cores distributed across the plurality of distinct chips, each of the plurality of multiprocessor cores configured to execute a single instruction to perform multiple matrix multiplication and accumulate operations;
wherein:
the matrix multiplication and accumulate operations comprise floating-point operations;
the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions, the two-dimensional matrix multiply and accumulate operations including a plurality of concurrent multiply operations;
the floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and
the first operation comprises a multiply having at least one 16-bit floating-point input and the second operation comprises an accumulate having a 32-bit floating-point input.
2. The multi-chip module accelerator of claim 1 , wherein the memory stack comprises high bandwidth memory.
3. The multi-chip module accelerator of claim 1 , wherein the memory stack is comprised in a same physical package as the parallel processor circuitry.
4. The multi-chip module accelerator of claim 1 , wherein each of the plurality of multiprocessor cores are digital processor cores.
5. The multi-chip module accelerator of claim 1 , wherein the first operation involves two or more 16-bit floating-point inputs.
6. The multi-chip module accelerator of claim 1 , wherein:
the multi-chip module accelerator is to be communicatively coupled to at least one accelerator cluster; and
the at least one accelerator cluster comprises identical parallel processors communicatively coupled together.
7. The multi-chip module accelerator of claim 1 , wherein:
the plurality of multiprocessor cores are to use a unified memory space associated with the memory stack.
8. At least one non-transitory machine-readable storage medium storing instructions for being executed by at least one machine associated with a multi-chip module accelerator, the multi-chip module accelerator comprising an interconnect to a host processor, a multi-chip module having a plurality of distinct chips integrated on the multi-chip module, a memory stack, and parallel processor circuitry, the parallel processor circuitry being communicatively coupled to the memory stack, the memory stack including multiple memory dies, the parallel processor circuitry comprising a plurality of multiprocessor cores distributed across the plurality of distinct chips, each of the plurality of multiprocessor cores configured to execute matrix multiplication and accumulate instructions, and the instructions, when executed by the at least one machine, result in the multi-chip module accelerator being configured for performance of operations comprising:
executing, by the plurality of multiprocessor cores, a single instruction to perform multiple matrix multiplication and accumulate operations;
wherein:
the matrix multiplication and accumulate operations comprise floating-point operations;
the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions, the two-dimensional matrix multiply and accumulate operations including a plurality of concurrent multiply operations;
the floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and
the first operation comprises a multiply having at least one 16-bit floating-point input and the second operation comprises an accumulate having a 32-bit floating-point input.
9. The at least one non-transitory machine-readable storage medium of claim 8 , wherein the memory stack comprises high bandwidth memory.
10. The at least one non-transitory machine-readable storage medium of claim 8 , wherein the memory stack is comprised in a same physical package as the parallel processor circuitry.
11. The at least one non-transitory machine-readable storage medium of claim 8 , wherein each of the plurality of multiprocessor cores are digital processor cores.
12. The at least one non-transitory machine-readable storage medium of claim 8 , wherein the first operation involves two or more 16 -bit floating-point inputs.
13. The at least one non-transitory machine-readable storage medium of claim 8 , wherein:
the multi-chip module accelerator is to be communicatively coupled to at least one accelerator cluster; and
the at least one accelerator cluster comprises identical parallel processors communicatively coupled together.
14. The at least one non-transitory machine-readable storage medium of claim 8 , wherein:
the plurality of multiprocessor cores are to use a unified memory space associated with the memory stack.
15. A method implemented using a multi-chip module accelerator, the multi-chip module accelerator comprising an interconnect to a host processor, a multi-chip module having a plurality of distinct chips integrated on the multi-chip module, a memory stack, and parallel processor circuitry, the parallel processor circuitry being communicatively coupled to the memory stack, the memory stack including multiple memory dies, the parallel processor circuitry comprising a plurality of multiprocessor cores distributed across the plurality of distinct chips, each of the plurality of multiprocessor cores configured to perform matrix multiplication and accumulate instructions, the method comprising:
executing, by the plurality of multiprocessor cores, a single instruction to cause the plurality of multiprocessor cores to perform multiple matrix multiplication and accumulate operations;
wherein:
the matrix multiplication and accumulate operations comprise floating-point operations;
the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions, the two-dimensional matrix multiply and accumulate operations including a plurality of concurrent multiply operations;
the floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and
the first operation comprises a multiply having at least one 16-bit floating-point input and the second operation comprises an accumulate having a 32-bit floating-point input.
16. The method of claim 15 , wherein the memory stack comprises high bandwidth memory.
17. The method of claim 15 , wherein the memory stack is comprised in a same physical package as the parallel processor circuitry.
18. The method of claim 15 , wherein each of the plurality of multiprocessor cores are digital processor cores.
19. The method of claim 15 , wherein the first operation involves two or more 16-bit floating-point inputs.
20. The method of claim 15 , wherein:
the multi-chip module accelerator is to be communicatively coupled to at least one accelerator cluster; and
the at least one accelerator cluster comprises identical parallel processors communicatively coupled together.
21. The method of claim 15 , wherein:
the plurality of multiprocessor cores are to use a unified memory space associated with the memory stack.
22. An accelerator cluster comprising:
identical parallel processors communicatively coupled together; and
a multi-chip module accelerator communicatively coupled to the identical parallel processors;
wherein:
the multi-chip module accelerator is usable to execute tensor data processing instructions;
the multi-chip module accelerator comprises a multi-chip module;
the multi-chip module comprises:
an interconnect to a host processor;
a plurality of distinct chips integrated on the multi-chip module;
a memory stack including multiple memory dies; and
parallel processor circuitry communicatively coupled to the memory stack;
the parallel processor circuitry comprises a plurality of multiprocessor cores distributed across the plurality of distinct chips, each of the plurality of multiprocessor cores configured to execute a single instruction to perform multiple matrix multiplication and accumulate operations;
the matrix multiplication and accumulate operations comprise floating-point operations;
the floating-point operations are configurable to comprise two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions, the plurality of floating-point operations including a plurality of concurrent multiply operations;
the plurality of floating-point operations comprise a first operation at a first precision and a second operation at a second precision; and
the first operation comprises a multiply having at least one 16-bit floating-point input and the second operation comprises an accumulate having a 32-bit floating-point input.
23. The accelerator cluster of claim 22 , wherein the memory stack comprises high bandwidth memory.
24. The accelerator cluster of claim 22 , wherein the memory stack is comprised in a same physical package as the parallel processor circuitry.
25. The accelerator cluster of claim 22 , wherein each of the plurality of multiprocessor cores are digital processor cores.
26. The accelerator cluster of claim 22 , wherein the first operation involves two or more 16-bit floating-point inputs.
27. The accelerator cluster of claim 22 , wherein:
the plurality of multiprocessor cores are to use a unified memory space associated with the memory stack.