Digital design simulation accelerator
A simulation acceleration system is provided. The system includes a simulation accelerator that receives compiled code of a design that includes register transfer level (RTL) components and testbench components. The compiled code includes instructions for simulating behaviors of the design. The simulation accelerator schedules the instructions to be executed by multiple processors based on simulation events occurring at different simulation timesteps. The simulation events are determined according to the executed instructions. The simulation accelerator captures trace data generated by the execution of the scheduled instructions and provides the captured trace data.
1 . A method comprising:
receiving source code of a design comprising register transfer level (RTL) code and testbench code;
compiling the source code into compiled code, the compiled code comprising instructions for simulating behaviors of the design, one or more first blocks, and one or more second blocks, wherein the one or more first blocks are statically sorted into levels such that blocks of a same level have no logical dependency with each other;
scheduling the instructions to be executed by a plurality of processors based on simulation events occurring at different simulation timesteps, wherein the simulation events are determined according to the executed instructions, and wherein instructions are scheduled so the instructions of the one or more first blocks are not executed in parallel with the instructions of the one or more second blocks;
capturing trace data generated by the execution of the scheduled instructions, the trace data comprising data captured from one or more memory ranges identified by the compiler; and
providing the captured trace data.
2 . The method of claim 1 , wherein the RTL codes of the design are compiled as the one or more one or more first blocks and at least some of the testbench code are compiled as the one or more second blocks.
3 . The method of claim 1 , wherein the instructions of the compiled code comprise one or more transactions, each transaction comprising one or more instructions designated as belonging to the transaction, wherein upon completion of the transaction, data generated by a first processor executing the transaction is committed to a heap memory and is aborted when an abort condition has occurred.
4 . The method of claim 3 , wherein the abort condition occurs when the first processor and a second processor have conflicting writes to their respective caches.
5 . The method of claim 3 , wherein the instructions of the one or more first are not executed as transactions.
6 . The method of claim 3 , wherein a particular transaction comprises an instruction that is deferred to execute until the particular transaction is committed to the heap memory.
7 . The method of claim 6 , wherein the deferred instruction mutates a global state and returns no result.
8 . The method of claim 3 , wherein when a first transaction and a second transaction are scheduled to be executed in a same timestep, the execution of the first transaction aborts and restarts after the second transaction is complete but in the same timestep.
9 . The method of claim 1 , wherein the compiled code comprises a plurality of prefetch sections that is defined by a compiler, wherein each prefetch section comprises a set of instructions that occupies a memory storage space that can fit within an instruction cache of a processor.
10 . The method of claim 9 , wherein the compiled code further comprises a set of prefetching directives that is determined based on relationships between logical blocks in the design by the compiler, the method further comprising identifying one or more prefetch sections according to the prefetching directives and prefetching the identified prefetch sections for the processor.
11 . The method of claim 1 , wherein the plurality of processors request memory allocations from a plurality of queues, each queue for storing pointers of memory allocations of a specific size, different queues correspond to memory allocations of different sizes.
12 . The method of claim 11 , further comprising reclaiming memory allocations that are leaked and replenishing the queues with pointers of the reclaimed memory allocations.
13 . The method of claim 1 , further comprising defining a plurality of prefetch sections in the compiled code, wherein each prefetch section comprises a set of instructions that occupies a memory storage space that can fit within an instruction cache of a processor, wherein the compiled code further comprises a set of prefetching directives that is determined based on relationships between logical blocks in the design, the method further comprising identifying one or more prefetch sections according to the prefetching directives and prefetching the identified prefetch sections for the processor.
14 . The method of claim 1 , wherein the plurality of processors request memory allocations from a plurality of queues, each queue for storing pointers of memory allocations of a specific size, different queues correspond to memory allocations of different sizes, the method further comprising reclaiming memory allocations that are leaked and replenishing the queues with pointers of the reclaimed memory allocations.