Low leakage FET
FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function Φ MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function Φ MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.
1. A method for fabricating an NMOSFET on a silicon-on-insulator substrate, including:
(a) forming an isolated silicon island;
(b) forming a gate structure overlying the isolated silicon island to define a central conduction channel, the central conduction channel having a length L and a threshold voltage Vt C , the gate structure having central and edge regions and including an N+ polysilicon layer having an associated work function Φ MF , wherein at least one edge transistor is defined by a corresponding edge region of the gate structure overlying the isolated silicon island, each edge transistor having a threshold voltage Vt E determined in part by the work function Φ MF of the polysilicon layer of the corresponding edge region of the gate structure;
(c) forming N+ source and drain regions within the isolated silicon island and defined by the gate structure and an implant mask configured to block implantation of N+ material over at least part of one edge region of the gate structure overlying the isolated silicon island; and
(d) forming a P+ implant region within the polysilicon layer of at least one corresponding edge region of the gate structure which increases the work function Φ MF of the polysilicon layer of such corresponding edge region of the gate structure sufficiently to increase the Vt E of such corresponding edge transistor to be approximately equal to or greater than Vt C .
2. The method of claim 1 , wherein the P+ implant region has a length L P less than or equal to length L.
3. The method of claim 1 , wherein the P+ implant region within such edge regions is triangular shaped.
4. The method of claim 1 , further including flaring at least one edge region of the gate structure to a length L + greater than length L to increase the Vt E of the corresponding edge transistor compared to Vt C .
5. The method of claim 1 , wherein the increase in the work function Φ MF and Vt E is at least about 0.3 V.
6. The method of claim 1 , further including forming a body tie to one of the source region, the gate structure, or an external node.
7. A method for fabricating an NMOSFET on a silicon-on-insulator substrate, including:
(a) forming an isolated silicon island on the silicon-on-insulator substrate;
(b) forming a gate structure overlying the isolated silicon island to define a central conduction channel having a center length L and a threshold voltage Vt C , the gate structure having central and edge regions each with an associated work function Φ MF , wherein at least one edge transistor is defined by a corresponding edge region of the gate structure overlying the isolated silicon island, each edge transistor having a threshold voltage Vt E determined in part by the work function Φ MF of the corresponding edge region of the gate structure;
(c) forming a source region and a drain region within the isolated silicon island and proximate to and defined by the gate structure; and
(d) increasing the work function ΦM F of at least one corresponding edge region of the gate structure sufficiently to increase the Vt E of such corresponding edge transistor to be approximately equal to or greater than Vt C .
8. The method of claim 7 , wherein increasing the work function Φ MF of the corresponding edge regions of the gate structure includes implanting a P dopant within a P implant region within such edge regions.
9. The method of claim 8 , wherein the P implant region has a length L P less than or equal to length L.
10. The method of claim 8 , wherein the P implant region within such edge regions is triangular shaped.
11. The method of claim 7 , wherein the gate structure includes an N+ polysilicon layer and increasing the work function Φ MF of the corresponding edge regions of the gate structure includes implanting a P dopant within the N+ polysilicon layer of such edge regions.
12. The method of claim 7 , further including flaring at least one edge region of the gate structure to a length L+ greater than length L to increase the Vt E of the corresponding edge transistor compared to Vt C .
13. The method of claim 7 , wherein the increase in the work function Φ MF and Vt E is at least about 0.3 V.
14. The method of claim 7 , further including forming a body tie to one of the source region, the gate structure, or an external node.
15. The method of claim 7 , wherein increasing the work function Φ MF of the corresponding edge regions of the gate structure includes forming a metal or metal-like region within the edge regions of the gate structure such that the work function Φ MF differs between the central and edge regions of the gate structure.
16. The method of claim 7 , wherein increasing the work function Φ MF of the corresponding edge portions of the gate structure includes forming the central region of the gate structure with a first metal or metal-like material, and forming the edge regions of the gate structure with a second metal or metal-like material, such that the work function Φ MF differs between the central and edge regions of the gate structure.
17. The method of claim 7 , wherein the gate structure is formed of polysilicon, and increasing the work function ΦMF of the corresponding edge portions of the gate structure includes doping the edge regions of the gate structure to form degeneratively-doped polysilicon, such that the work function Φ MF differs between the central and edge regions of the gate structure.
18. The method of claim 7 , wherein increasing the work function Φ MF of the corresponding edge portions of the gate structure includes doping an insulator beneath the gate structure, such that the work function Φ MF differs between the central and edge regions of the gate structure.
19. The method of claim 7 , wherein increasing the work function Φ MF of the corresponding edge portions of the gate structure includes forming the central region of the gate structure from a material having a first dopant, and modifying the edge regions of the gate structure with a second dopant, such that the work function Φ MF differs between the central and edge regions of the gate structure.
20. A method for fabricating an NMOSFET on a silicon-on-insulator substrate, including:
(a) forming an isolated silicon island;
(b) forming a gate structure overlying the isolated silicon island to define a central conduction channel having a center length L and a threshold voltage Vt C , the gate structure having central and edge regions each with an associated work function Φ MF , wherein at least one edge transistor is defined by a corresponding edge region of the gate structure overlying the isolated silicon island, each edge transistor having a threshold voltage Vt E determined in part by the work function Φ MF of the corresponding edge region of the gate structure, and wherein the gate structure includes an N+ polysilicon layer;
(c) forming source and drain regions within the isolated silicon island and defined by the gate structure; and
(d) increasing the work function ΦM F of at least one corresponding edge region of the gate structure sufficiently to increase the Vt E of such corresponding edge transistor to be approximately equal to or greater than Vt C , wherein increasing the work function Φ MF of the corresponding edge regions of the gate structure includes implanting a P dopant within the N+ polysilicon layer of such edge regions.