Bolometer unit cell pixel integrity check systems and methods
Techniques to test infrared detectors are disclosed. In one example, a focal plane array for an imaging system includes a plurality of infrared detectors arranged in a plurality of rows and columns where each of the infrared detectors is configured to provide an output signal in response to externally received thermal radiation associated with a scene. A plurality of offset circuits of the imaging system may be electrically coupled to the focal plane array and configured to selectively superimpose fixed-pattern noise on the output signals to provide modified output signals. A readout integrated circuit of the imaging system may be configured to provide the modified output signals for processing to test an integrity of the infrared detectors. Modified output signals that are outside an expected output range based on the thermal radiation and known offset may be determined defective. Related methods, devices, and systems are also provided.
1. A system comprising:
a focal plane array comprising a plurality of infrared detectors arranged in a plurality of rows and columns, wherein each of the infrared detectors is configured to provide an output signal in response to externally received thermal radiation;
a plurality of offset circuits electrically coupled to the focal plane array and configured to selectively superimpose fixed-pattern noise on the output signals to provide modified output signals;
a readout integrated circuit configured to provide the modified output signals for processing by a logic device; and
the logic device configured to perform the processing for each of the modified output signals by operating to:
compare the modified output signal to an expected output range associated with the thermal radiation and the fixed-pattern noise, and
identify the infrared detector corresponding to the modified output signal as defective if the modified output signal is outside the expected output range.
2. The system of claim 1 , wherein the logic device is further configured to:
determine a value associated with the fixed-pattern noise based on a temperature associated with the focal plane array;
determine a known value associated with the thermal radiation based on a previous image frame captured while the offset circuits were disabled; and
calculate the expected output range based on the known value associated with the thermal radiation and the value associated with the fixed-pattern noise.
3. The system of claim 1 , wherein each of the offset circuits comprises:
a resistor; and
a switch in parallel with the resistor and configured to selectively direct a current passed by at least one of the infrared detectors through the resistor to selectively superimpose the fixed-pattern noise on the output signal.
4. The system of claim 1 , wherein each of the offset circuits comprises a transistor configured to selectively adjust a current passed by at least one of the infrared detectors through the transistor to selectively superimpose the fixed-pattern noise on the output signal.
5. The system of claim 1 , wherein each of the offset circuits is in series with a corresponding one of the infrared detectors in a corresponding unit cell disposed in the focal plane array.
6. The system of claim 1 , further comprising:
a plurality of column read lines configured to pass the output signals from the infrared detectors; and
wherein each of the offset circuits is in series with a corresponding one of the column read lines and is configured to modify the output signals of the infrared detectors associated with the corresponding column read line.
7. The system of claim 1 , wherein:
the offset circuits comprise:
the logic device,
a memory comprising adjustment bits, and
circuit paths configured to provide the adjustment bits to a circuit component in electrical communication with the focal plane array; and
the logic device is configured to selectively update the adjustment bits to adjust an operation of the circuit component to selectively superimpose the fixed-pattern noise on the output signals.
8. The system of claim 7 , wherein the circuit component comprises:
a buffer configured to provide a reference voltage level to an amplifier configured to receive a signal from at least one of the infrared detectors;
the amplifier; and/or
a digital-to-analog converter (DAC) configured to adjust a bias voltage of one or more of the infrared detectors.
9. A method of operating the system of claim 1 , the method comprising:
activating the offset circuits to superimpose the fixed-pattern noise;
reading out the modified output signals;
operating the logic device to perform the processing; and
enabling a correction adjustment for the infrared detectors identified as defective, wherein the correction adjustment replaces future output signals read out from the defective infrared detectors.
10. A method comprising:
receiving external thermal radiation onto a focal plane array comprising a plurality of infrared detectors arranged in a plurality of rows and columns and configured to receive the external thermal radiation and provide an output signal in response to the externally received thermal radiation;
selectively superimposing fixed-pattern noise on the output signals to provide modified output signals, wherein the superimposing is performed using a plurality of offset circuits electrically coupled to the focal plane array and configured to selectively superimpose the fixed-pattern noise on the output signals to provide the modified output signals;
reading out the modified output signal from each of the infrared detectors of the focal plane array in a row-by-row fashion for processing by a logic device, wherein the reading is performed using a readout integrated circuit electrically coupled to the focal plane array;
comparing, using the logic device, the modified output signal to an expected output range associated with the thermal radiation and the fixed-pattern noise; and
identifying, using the logic device, the infrared detector corresponding to the modified output signal as defective if the modified output signal is outside the expected output range.
11. The method of claim 10 , further comprising:
determining, using the logic device, a value associated with the fixed-pattern noise based on a temperature associated with the focal plane array;
determining a known value associated with the thermal radiation based on a previous image frame captured while the offset circuits were disabled; and
calculating, using the logic device, the expected output range based on the known value associated with the thermal radiation and the determined value associated with the fixed-pattern noise.
12. The method of claim 10 , further comprising:
enabling a correction adjustment for the infrared detectors identified as defective, wherein the correction adjustment replaces future output signals read out from the defective infrared detectors.
13. The method of claim 10 , wherein each of the offset circuits comprises:
a resistor; and
a switch in parallel with the resistor and configured to selectively direct a current passed by at least one of the infrared detectors through the resistor to selectively superimpose the fixed-pattern noise on the output signal.
14. The method of claim 10 , wherein each of the offset circuits comprises a transistor configured to selectively adjust a current passed by at least one of the infrared detectors through the transistor to selectively superimpose the fixed-pattern noise on the output signal.
15. The method of claim 10 , wherein each of the offset circuits is in series with a corresponding one of the infrared detectors in a corresponding unit cell disposed in the focal plane array.
16. The method of claim 10 , wherein:
the focal plane array further comprises a plurality of column read lines configured to pass the output signals from the infrared detectors; and
each of the offset circuits is in series with a corresponding one of the column read lines and is configured to modify the output signals of the infrared detectors associated with the corresponding column read line.
17. The method of claim 10 , wherein:
the offset circuits comprise:
the logic device,
a memory comprising adjustment bits, and
circuit paths configured to provide the adjustment bits to a circuit component in electrical communication with the focal plane array; and
the method further comprising:
selectively updating the adjustment bits by the logic device,
providing the updated adjustment bits to the circuit component over the circuit paths, and
adjusting an operation of the circuit component in response to the updated adjustment bits to selectively superimpose the fixed-pattern noise on the output signals.
18. The method of claim 17 , wherein the circuit component comprises:
a buffer configured to provide a reference voltage level to an amplifier configured to receive a signal from at least one of the infrared detectors;
the amplifier; and/or
a digital-to-analog converter (DAC) configured to adjust a bias voltage of one or more of the infrared detectors.
19. The system of claim 1 , wherein:
the readout integrated circuit is further configured to convert the modified signal to a digital value; and
the expected output range comprises an expected output range of digital values.
20. The method of claim 10 , further comprising:
converting, using the readout integrated circuit, the modified signal to a digital value, wherein the expected output range comprises an expected output range of digital values.