Granted Patent B1

US 12,218,497 · App. 17/964,772 · Granted Feb 4, 2025

Inventors: Gregory Pickrell (Rio Rancho, NM); Jason Christopher Neely (Albuquerque, NM); Lee Gill (Albuquerque, NM); Jacob Mueller (Albuquerque, NM); Luciano Andres Garcia Rodriguez (Albuquerque, NM); Jack David Flicker (Albuquerque, NM); Emily Ann Schrock (Albuquerque, NM); Robert Kaplar (Albuquerque, NM); Harold P. Hjalmarson (Albuquerque, NM); Jane Lehr (Placitas, NM)

Assignees: National Technology & Engineering Solutions of Sandia, LLC; UNM Rainforest Innovations

H02H9/02H02H1/0007

Abstract

Claims (66)

1. A switching apparatus having a power input terminal for electric power and a load terminal for connection to a load, comprising:

a transistor switch circuit connected between the power input terminal and the load terminal; and

a switchable bypass leg connected to the power input terminal and bypassing the transistor switch circuit, the switchable bypass leg including a series-connected photoconductive semiconductor switch (PCSS);

wherein the switchable bypass leg is configured to be optically switchable by the PCSS;

wherein the transistor switch circuit comprises:

at least a first plurality of n series-connected transistors, each of said transistors having a respective source terminal, a respective drain terminal, and a respective gate terminal, wherein for n a positive integer at least 3, the first plurality of n series-connected transistors includes a first transistor herein denominated J 1 , a last transistor herein denominated J n , and at least one transistor herein denominated J i , i having respective positive integer values between 1 and n;

a terminal S connected to the J 1 source terminal;

a terminal D connected to the J n drain terminal;

a control terminal G connected to the J 1 gate terminal; and

a dedicated voltage-balancing network connected between terminal S and terminal D; and

wherein the dedicated voltage-balancing network includes a number, at least two, of parallel-connected resistive legs, each parallel-connected resistive leg includes two or more series-connected resistors, and for each transistor after J 1 , the gate terminal connects to one of the parallel-connected resistive legs such that the parallel-connected resistive legs collectively constitute a voltage divider for dividing voltage across the n series-connected transistors.

2. The switching apparatus of claim 1 , the transistor switch circuit further comprising at least one partial transistor stack, wherein:

each said partial transistor stack comprises a number p of series-connected transistors that is at least 1 but less than n; and

each said partial transistor stack is connected in parallel across the transistors J 1 to J p of a respective plurality of n series-connected transistors.

3. The switching apparatus of claim 1 , wherein the switchable bypass leg includes a capacitor series-connected with the PCSS.

4. The switching apparatus of claim 1 , wherein the switching apparatus further comprises:

a load current sensor configured to measure a load current exiting the load terminal; and

a controller, the controller being connected to the load current sensor and configured to receive, from the load current sensor, a signal S(I L ) indicative of a load current, the controller configured to infer the presence of a hard fault condition from the signal S(I L ) and to declare an instant-trip state in response thereto, and the controller being configured to, when in the instant-trip state, first open the transistor switch circuit and then close the switchable bypass leg to enable conduction of a bypass current in the switchable bypass leg when the hard fault condition is inferred.

5. The switching apparatus of claim 4 , wherein:

the apparatus is further configured to enter a no-trip state, a delayed-trip state, or an instant-trip state, depending on the signal S(I L );

when the hard fault condition is inferred, the controller is configured to cause the apparatus to enter the instant-trip state; and

the controller is further configured such that:

opening of the transistor switch circuit is not permitted in the no-trip state;

opening of the transistor switch circuit is permitted in the delayed-trip state only when the load current is within a predetermined range of currents; and

opening of the transistor switch circuit occurs in the instant-trip state when the hard fault condition is inferred.

6. The switching apparatus of claim 5 , wherein the controller is configured such that opening of the transistor switch circuit in the delayed-trip state occurs after a time interval in which a cumulative amount of electrothermal energy determined from the signal S(I L ) reaches a predetermined energy threshold.

7. The switching apparatus of claim 4 further comprising an optical source, wherein:

the controller is configured to close the switchable bypass leg by sending a trigger signal to turn ON the optical source, the optical source configured to switch closed the PCSS; and

the controller is further configured to send the trigger signal at a specified time after the opening of the transistor switch circuit.

8. The switching apparatus of claim 4 , wherein:

the controller is configured to close the switchable bypass leg by sending a trigger signal to turn ON an optical source for switching closed the PCSS; and

the controller is further configured to send the trigger signal at a specified time after the opening of the transistor switch circuit.

9. The switching apparatus of claim 8 , wherein:

the PCSS has a voltage threshold for a high-gain mode; and

the specified time is a time when a voltage across the PCSS is above the voltage threshold for the high-gain mode.

10. The switching apparatus of claim 1 , wherein the switchable bypass leg further includes a capacitor series-connected to the PCSS and to the load terminal.

11. The switching apparatus of claim 1 , wherein the switchable bypass leg further includes a capacitor series-connected to the PCSS and to ground, the switchable bypass leg thereby bypassing the load terminal.

12. The switching apparatus of claim 1 , wherein the at least a first plurality of n series-connected transistors is at least a first plurality of n series-connected JFETs.

13. A method, comprising, in a power circuit:

sensing an electric current I on an input path directed to a load terminal for connecting to a load;

detecting whether the sensed electric current I is in a fault condition;

opening a transistor switch circuit in response to a detection of a fault condition, resulting in breaking of the input path directed to the load terminal; and

then closing a photoconductive semiconductor switch (PCSS), resulting in diverting the electric current onto a switchable bypass path that bypasses the transistor switch circuit;

wherein:

the opening of the transistor switch circuit comprises turning OFF a normally-ON transistor switch circuit;

the transistor switch circuit comprises at least one cascaded series of three or more transistors, including a bottom transistor at a bottom end of the series and a top transistor at a top end of the series;

in each said cascaded series, a terminal S is connected to a source terminal of the bottom transistor, and a terminal D is connected to a drain terminal of the top transistor; and

for each said cascaded series, a dedicated voltage-balancing network comprising at least two parallel-connected resistive legs is connected between terminal S and terminal D as a voltage divider for dividing voltage across the cascaded series, each parallel-connected resistive leg comprising two or more series-connected resistors.

14. The method of claim 13 , wherein:

the method further comprises declaring, in response to the sensing of the electric current I, one of a no-trip state, a delayed-trip state, or an instant-trip state;

the opening of the transistor switch circuit is not permitted from the no-trip state;

from the delayed-trip state, the opening of the transistor switch circuit is permitted only when the sensed electric current I is within a predetermined range of currents; and

the opening of the transistor switch circuit occurs upon declaring the instant-trip state.

15. The method of claim 14 , wherein:

the method further comprises, when in the delayed-trip state, computing a cumulative amount of electrothermal energy in response to the sensing of the electric current I;

the method further comprises, when in the delayed-trip state, determining if the cumulative amount of electrothermal energy has reached a delayed-trip trigger threshold; and

the opening of the transistor switch circuit from the delayed-trip state occurs upon determination that the cumulative amount of electrothermal energy has reached the delayed-trip trigger threshold.

16. The method of claim 15 , wherein the said states of the controller are responsive to a comparison of the sensed electric current I to a first current threshold Θ 1 and to a second current threshold Θ 2 greater than Θ 1 , such that for I<Θ 1 , the no-trip state is a stable state of the controller, for i<I<Θ 2 , the delayed-trip state is a stable state of the controller until the delayed-trip trigger threshold is reached, and for I at least Θ 2 , the instant-trip state is declared.

17. The method of claim 13 , wherein:

the closing of the PCSS comprises sending a trigger signal to turn ON an optical source for switching closed the PCSS; and

the trigger signal is sent at a predetermined time after the opening of the transistor switch circuit.

18. The method of claim 17 , wherein:

the PCSS has a voltage threshold for a lock-on mode of operation; and

the predetermined time for sending the trigger signal is a time when a voltage across the PCSS is above the voltage threshold for the lock-on mode.

19. The method of claim 13 , wherein the switchable bypass path passes through a capacitor to the load terminal.

20. The method of claim 13 , wherein the switchable bypass path passes through a capacitor to ground and bypasses the load terminal.

Assignments (4)

Continuity (1)

References Cited (59)

Cited By (2)

US 12,340,994 US 12,706,606