Bipolar-CMOS-DMOS semiconductor device having a deep trench isolation structure for high isolation breakdown voltage
A semiconductor device including: a semiconductor substrate including a buried layer; and a deep trench isolation a predetermined depth disposed starting from an upper surface of the semiconductor substrate, wherein the deep trench isolation includes: a first point disposed near the upper surface of the semiconductor substrate; a second point disposed near the buried layer; and a third point disposed near a bottom face of the deep trench isolation, and wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point, is disclosed.
1. A semiconductor device comprising:
a semiconductor substrate comprising a buried layer; and
a deep trench isolation a predetermined depth disposed starting from an upper surface of the semiconductor substrate,
wherein the deep trench isolation comprises:
a first point disposed near the upper surface of the semiconductor substrate;
a second point disposed near the buried layer; and
a third point disposed near a bottom face of the deep trench isolation, and
wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point.
2. The semiconductor device of claim 1 ,
wherein the second point is disposed in contact with the buried layer.
3. The semiconductor device of claim 1 ,
wherein a width of the deep trench isolation at the third point is at least about 1.2 times greater than a width of the deep trench isolation at the first point.
4. The semiconductor device of claim 1 ,
wherein an angle of the inclination of the deep trench isolation is about 91° to 100° with respect to the upper surface of the semiconductor substrate.
5. The semiconductor device of claim 1 ,
wherein TEOS oxide film or borophosphosilicate glass (BPSG) film is disposed inside the deep trench isolation.
6. The semiconductor device of claim 1 ,
wherein an air gap is disposed between the second point and the third point.
7. The semiconductor device of claim 1 ,
wherein the predetermined depth of the deep trench isolation is greater than a depth of the buried layer.
8. The semiconductor device of claim 1 ,
wherein the predetermined depth of the deep trench isolation is about 20 μm to 30 μm.
9. The semiconductor device of claim 1 ,
wherein a width of the deep trench isolation is about 1.6 μm to 4 μm.
10. The semiconductor device of claim 1 ,
wherein a first percentage of a first distance from the upper surface of the semiconductor substrate to the first point based on a total depth of the deep trench isolation is 1 to 10%, a second percentage of a second distance from the upper surface of the semiconductor substrate to the second point based on the total depth of the deep trench isolation is 20 to 35%, and a third percentage of a third distance from the upper surface of the semiconductor substrate to the third point based on the total depth of the deep trench isolation is 90 to 100%, respectively.
11. A semiconductor device comprising:
a semiconductor substrate comprising a highly doped buried layer;
a deep trench isolation with a predetermined depth disposed starting from an upper surface of the semiconductor substrate,
wherein the deep trench isolation comprises:
a first point disposed near the upper surface of semiconductor substrate;
a second point disposed overlapping with the highly doped buried layer;
a third point disposed near a bottom face of the deep trench isolation;
an air gap disposed between the second point and the third point; and
a gap-fill insulating film surrounding the air gap, and
wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point.
12. The semiconductor of claim 11 ,
wherein the predetermined depth of the deep trench isolation is greater than a depth of the highly doped buried layer.
13. The semiconductor device of claim 11 ,
wherein the predetermined depth of the deep trench isolation is about 20 μm to 30 μm.
14. The semiconductor device of claim 11 ,
wherein a width of the deep trench isolation is about 1.6 μm to 4 μm.
15. The semiconductor device of claim 11 ,
wherein an angle of the inclination of the deep trench isolation between the second point and the third point is about 91° to 100° with respect to the upper surface of the semiconductor substrate.
16. The semiconductor device of claim 11 ,
wherein the semiconductor substrate further comprises an epi layer disposed on the highly doped buried layer.
17. The semiconductor device of claim 11 ,
wherein a first percentage of a first distance from the upper surface of the semiconductor substrate to the first point based on a total depth of the deep trench isolation is 1 to 10%, a second percentage of a second distance from the upper surface of the semiconductor substrate to the second point based on the total depth of the deep trench isolation is 20 to 35%, and a third percentage of a third distance from the upper surface of the semiconductor substrate to the third point based on the total depth of the deep trench isolation is 90 to 100%, respectively.