Pixel architecture with multiple pixel binning
Structures are disclosed for a binned set of two or more pixels of a pixel array that share a same readout circuit. The binned pixel design provides space-saving benefits on the chip and also improves the overall image quality. According to some embodiments, each of the binned pixels includes a photodetector and its own transfer gate. The readout circuit is coupled to the transfer gates of each of the binned pixels and includes its own second transfer gate that separates the pixels from a gain mode select block. The gain mode select block may include capacitors of different sizes and one or more switches to control which capacitors are to receive the charge from any one of the binned pixels. The readout circuit may also include a potential barrier (such as a diode), which allows for pumping charge onto the one or more capacitors of the gain mode select block.
1. A charge coupled device (CCD), comprising:
a first pixel and a second pixel, with each of the first and second pixels including a photodetector and a corresponding first transfer gate coupled to the photodetector;
a second transfer gate having an input coupled to an output of each first transfer gate of the first and second pixels;
a potential barrier coupled to an output of the second transfer gate; and
a capacitor coupled to the output of the second transfer gate;
wherein the capacitor is a first capacitor and the CCD comprises a second capacitor and a switch coupled between the output of the second transfer gate and the second capacitor; and
wherein the second capacitor has a higher capacitance than the first capacitor.
2. The CCD of claim 1 , wherein the corresponding first transfer gate of each of the first and second pixels is a field effect transistor (FET).
3. The CCD of claim 1 , further comprising a reset switch coupled to a shared node between the switch and the second capacitor.
4. The CCD of claim 1 , wherein the potential barrier is a PN diode.
5. The CCD of claim 1 , wherein the output of the second transfer gate is coupled to a gate of a FET.
6. The CCD of claim 1 , wherein the first and second pixels are arranged in a 2×2 grid that comprises four pixels.
7. An image sensor, comprising:
a pixel array having at least one column of addressable pixels, wherein the at least one column of addressable pixels includes at least two pixels with each pixel of the at least two pixels including a photodetector and a corresponding first transfer gate coupled to the photodetector;
a readout circuit;
a column amplifier coupled to the readout circuit;
an analog-to-digital converter (ADC) coupled to the column amplifier; and
a processor coupled to the ADC;
wherein the readout circuit comprises
a second transfer gate having an input coupled to an output of each first transfer gate of each of the at least two pixels,
a potential barrier coupled to an output of the second transfer gate, and
a capacitor coupled to the output of the second transfer gate;
wherein the capacitor is a first capacitor and the readout circuit comprises a second capacitor and a switch coupled between the output of the second transfer gate and the second capacitor; and
wherein the second capacitor has a higher capacitance than the first capacitor.
8. The image sensor of claim 7 , wherein the readout circuit further comprises a reset switch coupled to a shared node between the switch and the second capacitor.
9. The image sensor of claim 7 , wherein the potential barrier is a PN diode.
10. The image sensor of claim 7 , wherein the at least two pixels comprises four pixels arranged in a 2×2 grid.
11. A charge coupled device (CCD), comprising:
four pixels with each pixel of the four pixels including a photodetector and a corresponding first transfer gate coupled to the photodetector;
a second transfer gate having a single input coupled to an output of each first transfer gate of each of the four pixels; and
a capacitor coupled to the output of the second transfer gate;
wherein the capacitor is a first capacitor and the CCD comprises a second capacitor and a switch coupled between the output of the second transfer gate and the second capacitor; and
wherein the second capacitor has a higher capacitance than the first capacitor.
12. The CCD of claim 11 , further comprising a reset switch coupled to a shared node between the switch and the second capacitor.
13. The CCD of claim 11 , wherein the output of the second transfer gate is coupled to a gate of a FET.
14. The CCD of claim 11 , wherein the four pixels are arranged in a 2×2 grid.