Image sensor pixels having built-in variable gain feedback amplifier circuitry
An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate. An amplifying transistor may have a gate terminal coupled to the floating diffusion and a drain terminal coupled to an output node. The amplifying transistor may provide signal corresponding to transferred charge with a greater than unity voltage gain. A negative voltage feedback capacitor having variable capacitance may be coupled between the output node and the floating diffusion node thereby increasing the pixel dynamic range. A reset transistor may be coupled between the floating diffusion and output node. The amplifying transistor may include a p-channel transistor formed within a mini n-well region of the pixel or an n-channel transistor formed within a mini p-well region. The pixel may have increased storage capacity and dynamic range relative to conventional designs.
1. An image sensor pixel, comprising:
a photodiode that generates charge in response to image light;
a floating diffusion node;
a charge transfer transistor configured to transfer the generated charge from the photodiode to the floating diffusion node;
an amplifying transistor having a drain terminal coupled to a pixel output node, wherein the floating diffusion node is coupled between a drain terminal of the charge transfer transistor and a gate terminal of the amplifying transistor;
a feedback capacitor coupled between the pixel output node and the floating diffusion node, wherein the amplifying transistor is configured to provide the transferred charge with a greater than unity gain and the feedback capacitor is configured to provide negative voltage feedback to the floating diffusion node; and
a pre-charge capacitor coupled between the floating diffusion node and a pre-charge bus line.
2. The image sensor pixel defined in claim 1 , further comprising:
a reset transistor coupled between the pixel output node and the floating diffusion node in parallel with the feedback capacitor, wherein the reset transistor is configured to reset the floating diffusion node to a reset voltage.
3. The image sensor pixel defined in claim 2 , further comprising:
a column readout line coupled to a column biasing current source; and
a pixel addressing transistor coupled between the pixel output node and the column readout line.
4. The image sensor pixel defined in claim 2 , wherein the reset transistor comprises an n-channel reset transistor and the amplifying transistor comprises a p-channel amplifying transistor.
5. The image sensor pixel defined in claim 4 , wherein the p-channel amplifying transistor has a source terminal coupled to a column bias voltage line.
6. The image sensor pixel defined in claim 4 , wherein the image sensor pixel is formed on a semiconductor substrate, further comprising:
a p-type doped epitaxial layer in the semiconductor substrate;
an n-type doped well region in the semiconductor substrate, wherein the p-channel amplifying transistor is formed within the n-type doped well region; and
a p+ type retrograde doped electron blocking layer in the semiconductor substrate that separates the n-type doped well region from the p-type doped epitaxial layer.
7. The image sensor pixel defined in claim 2 , wherein the reset transistor comprises a p-channel reset transistor and the amplifying transistor comprises an n-channel amplifying transistor.
8. The image sensor pixel defined in claim 1 , wherein the amplifying transistor comprises an n-channel amplifying transistor and wherein the image sensor pixel is formed on a semiconductor substrate, the image sensor pixel further comprising:
an n-type doped epitaxial layer in the semiconductor substrate;
a p-type doped well region in the semiconductor substrate, wherein the n-channel amplifying transistor is formed within the p-type doped well region; and
an n+ type retrograde doped electron blocking layer in the semiconductor substrate that separates the p-type doped well region from the n-type doped epitaxial layer.
9. The image sensor pixel defined in claim 1 , wherein the feedback capacitor has a variable capacitance that depends on a potential difference between the gate terminal of the amplifying transistor and the drain terminal of the amplifying transistor.
10. The image sensor pixel defined in claim 1 , wherein the image sensor pixel is formed on a semiconductor substrate, further comprising:
pixel isolation regions selected from a group consisting of: shallow trench isolation regions and deep trench isolation regions, wherein the pixel isolation regions are configured to isolate the photodiode from other photodiodes on the semiconductor substrate.
11. The image sensor pixel defined in claim 1 , wherein the image sensor pixel is formed on a semiconductor substrate having opposing front and back sides, wherein the photodiode is configured to generate the charge in response to image light received through the back side of the semiconductor substrate.
12. The image sensor pixel defined in claim 1 , wherein the image sensor pixel is formed on a semiconductor substrate, wherein the semiconductor substrate is coupled to an additional semiconductor substrate, wherein a bias current source for the image sensor pixel is formed on the additional semiconductor substrate, and wherein the pixel output node is coupled to the bias current source on the additional semiconductor substrate through a conductive via.
13. An image sensor pixel formed on a semiconductor substrate, comprising:
a photosensitive region;
a charge storage region configured to store charge generated by the photosensitive region;
a transistor having a gate terminal coupled to the charge storage region and a drain terminal coupled to a pixel output node, wherein the transistor is configured to provide a gain greater than unity to signals transferred to the pixel output node;
a negative voltage feedback capacitor coupled between the pixel output node and the charge storage region;
a row select transistor coupled between the pixel output node and a column readout line, wherein a source terminal of the row select transistor is coupled to the pixel output node;
a reset transistor coupled between the pixel output node and the charge storage region; and
a current source coupled to a drain terminal of the row select transistor.
14. The image sensor pixel defined in claim 13 , wherein the negative voltage feedback capacitor has a variable capacitance dependent upon a potential difference between the gate and the drain of the transistor.
15. The image sensor pixel defined in claim 13 , wherein the transistor comprises a first p-channel metal-oxide-semiconductor field-effect transistor (MOSFET), the row select transistor comprises a second p-channel MOSFET, and the reset transistor comprises an n-channel MOSFET.
16. The image sensor pixel defined in claim 13 , wherein the transistor comprises a first n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), the row select transistor comprises a second n-channel MOSFET, and the reset transistor comprises a p-channel MOSFET.
17. A system, comprising: a central processing unit; memory; input-output circuitry; and an imaging device, wherein the imaging device comprises:
a pixel array having at least one pixel circuit, and a lens that focuses an image onto the pixel array, wherein the pixel array comprises a semiconductor substrate and an n-type doped well region in the semiconductor substrate, wherein the at least one pixel circuit comprises:
a photodiode that generates charge in response to image light;
a floating diffusion region;
a charge transfer transistor configured to transfer the generated charge from the photodiode to the floating diffusion node;
a p-channel gain transistor having a gate terminal coupled to the floating diffusion node and a drain terminal coupled to a pixel output node, wherein the p-channel gain transistor is formed in the n-type doped well region, wherein the drain terminal is formed from a P+ type doped region in the n-type doped well region that is adjacent to the p-channel gain transistor;
a p-type doped extension region that is formed in the n-type doped well region adjacent to the p-channel gain transistor and the P+ type doped region, wherein the p-type doped extension region extends under a gate terminal of the p-channel gain transistor;
a feedback capacitor coupled between the pixel output node and the floating diffusion region, wherein the p-channel gain transistor is configured to provide the transferred charge with a gain that is greater than one and the feedback capacitor is configured to provide negative voltage feedback to the floating diffusion node; and
an n-channel reset transistor coupled between the pixel output node and the floating diffusion region in parallel with the feedback capacitor.