IP Library Granted Patent US 12,584,856
Granted Patent B2
US 12,584,856 · App. 17/967,627 · Granted Mar 24, 2026

Dust sensor

Inventors: Suhwan Kim (Seoul, KR); Hyunjoong Lee (Daejeon, KR); Hyunjong Kim (Seoul, KR)
Assignees: Gwanak Analog CO., LTD.; Seoul National University R&DB Foundation
G01N21/47G01N2021/4733G01N2201/123
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Quick Facts
Patent No.
US 12,584,856
App. No.
17/967,627
Granted
Mar 24, 2026
Kind
B2
Abstract

A dust sensor includes a photo detector configured to detect light scattered from dust; and a signal processing circuit having a high-pass filter receiving an electric signal generated from output of the photo detector. The signal processing circuit generates a dust detection signal using a signal provided to the high-pass filter as well as a signal output from the high-pass filter.

Claims (22)

1 . A dust sensor comprising:

a photo detector configured to detect light scattered from dust; and

a signal processing circuit including a high-pass filter receiving an electric signal generated from output of the photo detector,

wherein the signal processing circuit generates a dust detection signal using a signal provided to the high-pass filter as well as a signal output from the high-pass filter,

wherein the signal processing circuit generates an offset signal in a dust-free state,

generates a signal corresponding to high density dust using the signal provided to the high-pass filter and the offset signal, and generates a signal corresponding to low density dust using output of the high-pass filter, wherein the signal corresponding to high density dust and the signal corresponding to low density dust are based on a size of the dust using magnitude, direction of change, or duration of the signal corresponding to high density dust and the signal corresponding to low density dust.

2 . The dust sensor of claim 1 , further comprising a transimpedance amplifier configured to generate the electric signal by transforming output of the photo detector into a voltage signal.

3 . The dust sensor of claim 1 , where in the signal processing circuit further includes:

an amplifier configured to amplify output of the high-pass filter;

an analog-to-digital converter (ADC) configured to convert the electric signal or output of the amplifier into a digital signal;

a high density dust information generating circuit configured to generate high density dust information from output of the ADC; and

a dust detection signal generating circuit configured to generate the dust detection signal corresponding to whole dust information from output of the ADC and the high density dust information.

4 . The dust sensor of claim 3 , further comprising a mux configured to provide the electric signal or output of the amplifier to the ADC.

5 . The dust sensor of claim 3 , further comprising a demux configured to provide output of the ADC to the high density dust information generating circuit or the dust detection signal generating circuit.

6 . The dust sensor of claim 3 , wherein the high density dust information generating circuit includes:

a low-pass filter configured to filter output of the ADC;

a first operation configured to multiply output of the low-pass filter by a gain signal;

a register configured to store output of the first operator; and

a second operator configured to subtract a value stored in the register from output of the first operator.

7 . The dust sensor of claim 6 , wherein the high density dust information generating circuit stores output of the first operator in the register in a dust-free state, and provides output of the second operator as the high density dust information in a dusty state.

8 . The dust sensor of claim 3 , wherein the dust detection signal generating circuit includes a third operator configured to add output of the ADC and output of the high density dust information generating circuit.

9 . The dust sensor of claim 8 , wherein the dust detection signal generating circuit further includes a detection circuit configured to generate the dust detection signal from output of the third operator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2022
From: KIM, SUHWAN; LEE, HYUNJOONG; KIM, HYUNJONG
To: GWANAK ANALOG CO., LTD.; SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
Reel/Frame 061445/0472 →
Priority Claims (1)
KR 10-2021-0139720 · Oct 19, 2021 · national
Continuity (1)
Related Publication 20230117076A1 · Apr 20, 2023
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