In-rush current protected power converter
Circuits and methods for protecting the switches of charge pump-based power converters from damage if a V OUT short circuit event occurs and/or if V IN falls rapidly with respect to V X or V OUT . A general embodiment includes a V X Detection Block coupled to the core block of a power converter. The V X Detection Block is coupled to V X and to a control circuit that disables operations of an associated converter circuit upon detection of large, rapid falls in V X during the dead time between clock phase signals, thereby prevent damaging current spikes. Some embodiments include a V IN Detection Block configured to detect and prevent excessive in-rush current due to rapidly falling values of V IN to the power converter. The V IN Detection Block is coupled to V IN , and to V X or V OUT in some embodiments, and to a control circuit to that disables operation of an associated converter circuit.
1. A power converter including:
(a) a converter circuit configured to convert an input voltage V IN to a different output voltage V OUT ;
(b) a control block for disabling operation of the converter circuit;
(c) a voltage node V X between the converter circuit and the output V OUT ;
(d) a V IN detection block, coupled to the input voltage V IN and to the control block, and optionally coupled to one of V OUT or the voltage node V X , and configured to detect a voltage drop in the input voltage V IN and generate a control signal to the control block to disable operation of the converter circuit;
wherein the converter circuit is coupled to a source of at least two non-overlapping clock signals having ON states separated by a dead time, and wherein the V IN detection block is configured to detect the voltage drop in the input voltage V IN during the dead time.
2. The power converter of claim 1 , wherein the V IN detection block is configured to detect a voltage drop in the input voltage V IN where the voltage drop has a magnitude that induces damage to the converter circuit.
3. The power converter of claim 1 , wherein the converter circuit, the control block, the voltage node V X , and the V IN detection block are embodied in a single integrated circuit die.
4. A power converter including:
(a) a converter circuit configured to convert an input voltage V IN to a different output voltage V OUT ;
(b) a control block for disabling operation of the converter circuit;
(c) a voltage node V X between the converter circuit and the output V OUT ;
(d) a V IN detection block, coupled to the input voltage V IN and to the control block, and optionally coupled to one of V OUT or the voltage node V X , and configured to detect a voltage drop in the input voltage V IN and generate a control signal to the control block to disable operation of the converter circuit, wherein the V IN detection block includes:
(1) a PMOS FET having a gate coupled to the voltage input V IN , a source, and a drain;
(2) a resistor coupled between the voltage input V IN and the source of the PMOS FET;
(3) a capacitor coupled between the source of the PMOS FET and a reference voltage;
(4) an inverter coupled to the drain of the PMOS FET; and
(5) a threshold voltage adjustment circuit coupled to the drain of the PMOS FET;
wherein the PMOS FET causes the inverter to generate the control signal if a voltage applied to the gate of the PMOS FET from the voltage input V IN has a voltage drop relative to a voltage across the capacitor.
5. The power converter of claim 4 , further including a degeneration resistor coupled between the capacitor and the source of the PMOS FET.
6. The power converter of claim 1 , wherein the V IN detection block further includes:
(a) a scaling circuit coupled to the input voltage V IN and configured to output a scaled output voltage;
(b) a comparator circuit, having a first input coupled to the scaled output voltage and a second input coupled to one of V OUT or the voltage node V X , and configured to output the control signal upon the occurrence of a voltage drop in the input voltage V IN relative to the voltage coupled to the second input.
7. A method for protecting a power converter, including:
(a) monitoring an input voltage V IN to a converter circuit of the power converter;
(b) applying a source of at least two non-overlapping clock signals having ON states separated by a dead time to the converter circuit; and
(c) disabling operation of the converter circuit upon detection of a voltage drop in the input voltage V IN during the dead time.
8. The method of claim 7 , wherein the voltage drop of the input voltage V IN has a magnitude that induces damage to the power converter.
9. The method of claim 7 , further including detecting a voltage drop in of the input voltage V IN relative to one of an output voltage V OUT of the power converter or a voltage node V X of the converter circuit.