MULTI-CHANNEL MEMORY MODULE
According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.
1 . A memory module comprising:
a printed circuit board (PCB) having a first face, a second face, and a first edge to be received by a connector;
a plurality of memory chips on at least one of the first and second faces of the PCB; and
two rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the first edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.
2 . The memory module of claim 1 , wherein:
the second row of conductive contacts is between the first row and the plurality of memory chips.
3 . The memory module of claim 1 , wherein:
the first row of conductive contacts is to couple with a plurality of inner pins of the connector; and
the second row of conductive contacts is to couple with a plurality of outer pins of the connector.
4 . The memory module of claim 1 , wherein:
the two rows of conductive contacts on each of the first and second faces of the PCB are to couple with two memory channels.
5 . The memory module of claim 4 , wherein:
the first and second rows of conductive contacts on the first face of the PCB are to couple with a first memory channel; and
the first and second rows of conductive contacts on the second face of the PCB are to couple with a second memory channel.
6 . The memory module of claim 4 , further comprising:
a single registering clock driver (RCD) on the PCB, the single RCD to receive command and address signals for both of the two memory channels.
7 . The memory module of claim 4 , further comprising:
a first registering clock driver (RCD) on the PCB to receive command and address signals for a first of the two memory channels; and
a second RCD on the PCB to receive command and address signals for a second of the two memory channels.
8 . The memory module of claim 7 , wherein:
the first RCD is on a first face of the PCB; and
the second RCD is on a second face of the PCB.
9 . The memory module of claim 1 , further comprising:
a third row of conductive contacts between the first row and the second row of conductive contacts.
10 . The memory module of claim 9 , wherein:
the first row of conductive contacts is to couple with a plurality of inner pins of the connector;
the second row of conductive contacts is to couple with a plurality of outer pins of the connector; and
the third row of conductive contacts is to couple with a plurality of pins between the plurality of inner pins and the plurality of outer pins.
11 . A dual-inline memory module (DIMM) comprising:
a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a DIMM connector;
a plurality of DRAM chips on each of the first and second faces of the PCB;
a bottom row of conductive contacts on each of the first and second faces of the PCB at the edge of the PCB to be received by the DIMM connector; and
a top row of conductive contacts on each of the first and second faces of the PCB, wherein the top row is aligned over and parallel to the bottom row of conductive contacts.
12 . The DIMM of claim 11 , wherein:
the top row of conductive contacts is between the bottom row and the plurality of DRAM chips.
13 . The DIMM of claim 11 , wherein:
the bottom row of conductive contacts is to couple with a plurality of inner pins of the DIMM connector; and
the top row of conductive contacts is to couple with a plurality of outer pins of the DIMM connector.
14 . The DIMM of claim 11 , wherein:
the bottom rows and the top rows of conductive contacts on each of the first and second faces of the PCB are to couple with two memory channels.
15 . The DIMM of claim 14 , wherein:
the bottom rows and the top rows of conductive contacts on the first face of the PCB are to couple with a first memory channel; and
the bottom rows and the top rows of conductive contacts on the second face of the PCB are to couple with a second memory channel.
16 . A system comprising:
a processor; and
a memory module coupled with the processor, the memory module including:
a printed circuit board (PCB) having a first face, a second face, and a first edge to be received by a connector;
a plurality of memory chips on at least one of the first and second faces of the PCB; and
two rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the first edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.
17 . The system of claim 16 , wherein:
the second row of conductive contacts is between the first row and the plurality of memory chips.
18 . The system of claim 16 , wherein:
the first row of conductive contacts is to couple with a plurality of inner pins of the connector; and
the second row of conductive contacts is to couple with a plurality of outer pins of the connector.
19 . The system of claim 16 , further comprising:
a motherboard including the connector.
20 . The system of claim 16 , further comprising:
one or more of: a display, a battery, and a power supply.