Granted Patent B2

US 12,449,830 · App. 17/970,033 · Granted Oct 21, 2025

Inventor: Alexandru-Valentin Craescu (Buchare, RO)

Assignee: Microchip Technology Incorporated

G05F1/563G05F1/561G05F1/575

Abstract

Claims (44)

1. An low dropout (LDO) regulator circuit comprising:

a pre-regulator circuit to receive a high voltage input voltage and provide a low voltage supply voltage; and

an LDO regulator to receive the low voltage supply voltage and provide a low voltage output voltage;

wherein the pre-regulator circuit comprises an input stage, an output stage coupled to the input stage, and a first MOSFET coupled to the output stage to provide the low voltage supply voltage, wherein the input stage, output stage, and first MOSFET receive the high voltage input voltage;

wherein the LDO regulator comprises a second MOSFET to receive the low voltage supply voltage and provide the low voltage output voltage;

wherein the first MOSFET is a high voltage n-type MOSFET and the second MOSFET is a low voltage p-type MOSFET;

wherein a source terminal of the first MOSFET is coupled to a source terminal of the second MOSFET, the low voltage supply voltage is provided at terminal of the first MOSFET, and the low voltage output voltage is provided at a drain terminal of the second MOSFET;

wherein the LDO regulator comprises a first amplifier and a second amplifier, to respectively receive the low voltage supply voltage;

wherein the first amplifier comprises an inverting input to receive a representation of the low voltage output voltage and a non-inverting input to receive a reference voltage;

wherein the second amplifier comprises a non-inverting input to receive an output of the first amplifier, and an inverting input to receive the low voltage output voltage; and

wherein the output of the second amplifier is coupled to gate terminal of the second MOSFET.

2. The LDO regulator circuit of claim 1 , wherein the LDO regulator comprises a voltage divider to divide the low voltage output voltage; and

wherein the inverting input of the first amplifier is to receive a divided low voltage output voltage from the voltage divider as the representation of the low voltage output voltage.

3. The LDO regulator circuit of claim 1 , wherein the input stage of the pre-regulator circuit is to receive the reference voltage.

4. A low dropout (LDO) regulator circuit comprising:

a pre-regulator circuit to receive a first high voltage input voltage and a second high voltage input voltage, and provide a low voltage supply voltage, the second high voltage input voltage greater than the first high voltage input voltage; and

an LDO regulator to receive the low voltage supply voltage and provide a low voltage output voltage;

wherein the pre-regulator circuit comprises an input stage, an output stage coupled to the input stage, and a first MOSFET coupled to the output stage to provide the low voltage supply voltage, wherein the input stage and a drain terminal of the first MOSFET receive the first high voltage input voltage, and the output stage receives the second high voltage input voltage; and

wherein the LDO regulator comprises a second MOSFET coupled to the first MOSFET to provide the low voltage output voltage;

wherein the first MOSFET is a high voltage n-type MOSFET and the second MOSFET is a low voltage p-type MOSFET,

wherein a source terminal of the first MOSFET is couple to a source terminal of the second MOSFET, the low voltage supply voltage is provided at the source terminal of the first MOSFET, and the low voltage output voltage is provided at a drain terminal of the second MOSFET

wherein the LDO regulator comprises a first amplifier and a second amplifier, to respectively receive the low voltage supply voltage;

wherein the first amplifier comprises an inverting input to receive the low voltage output voltage and a non-inverting input to receive a reference voltage;

wherein the second amplifier comprises a non-inverting input to receive an output of the first amplifier, and an inverting input to receive the low voltage output voltage; and

wherein the output of the second amplifier is coupled to gate terminal of the second MOSFET.

5. The LDO regulator circuit of claim 4 , wherein the LDO regulator comprises a voltage divider to divide the low voltage output voltage; and

wherein the inverting input of the first amplifier is to receive a divided low voltage output voltage from the voltage divider.

6. A method for regulating voltage in a low dropout (LDO) regulator circuit, the method comprising:

receiving a high voltage input voltage at a pre-regulator circuit;

generating a low voltage supply voltage using the pre-regulator circuit, wherein the pre-regulator circuit comprises:

an input stage;

an output stage coupled to the input stage; and

a first MOSFET coupled to the output stage to provide the low voltage supply voltage, wherein the input stage, output stage, and first MOSFET receive the high voltage input voltage;

supplying the low voltage supply voltage to an LDO regulator;

generating a low voltage output voltage using the LDO regulator, wherein the LDO regulator comprises a second MOSFET to receive the low voltage supply voltage and provide the low voltage output voltage;

providing a divided low voltage output voltage to an inverting input of a first amplifier, said divided low voltage provided from a voltage divider coupled to the second terminal of the second MOSFET, and a reference voltage to a non-inverting input of the first amplifier;

providing an output of the first amplifier to a non-inverting input of a second amplifier, and the low voltage output voltage to an inverting input of the second amplifier; and

controlling a gate voltage of the second MOSFET based on an output of the second amplifier.

7. The method of claim 6 , wherein the first MOSFET is a high voltage n-type MOSFET and the second MOSFET is a low voltage p-type MOSFET.

8. The method of claim 6 , wherein the first MOSFET is a high voltage n-type MOSFET and the second MOSFET is a low voltage n-type MOSFET.

9. The method of claim 6 , further comprising:

in response to an increase in a load receiving the low voltage output voltage, controlling the gate voltage of the second MOSFET to generate an increased load current at the second terminal of the second MOSFET.

10. The method of claim 6 , further comprising providing a second high voltage input voltage to circuit driving a gate terminal of the first MOSFET;

wherein the second high voltage input voltage is greater than the first high voltage input voltage.

Assignments (1)

Continuity (2)

References Cited (9)