Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same
Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.
1. A memory system, comprising:
a first memory device comprising:
first impedance adjustment circuitry configured to provide a first controllable impedance to a first clock signal having a first clock impedance; and
second impedance adjustment circuitry configured to provide a second controllable impedance to a second clock signal having a second clock impedance; and
a second memory device comprising:
third impedance adjustment circuitry configured to provide a third controllable impedance to the first clock signal, wherein the first controllable impedance and the third controllable impedance have a first combined controllable impedance that is based at least in part on the first clock impedance; and
fourth impedance adjustment circuitry configured to provide a fourth controllable impedance to the second clock signal, wherein the second controllable impedance and the fourth controllable impedance have a second combined controllable impedance that is based at least in part on the second clock impedance.
2. The memory system of claim 1 , wherein the first controllable impedance and the third controllable impedance are greater than the first clock impedance and wherein the second controllable impedance and the fourth controllable impedance are greater than the second clock impedance.
3. The memory system of claim 1 , wherein:
the first combined controllable impedance is greater than or equal to the first clock impedance based at least in part on the first impedance adjustment circuitry and the third impedance adjustment circuitry being connected in parallel, and
the second combined controllable impedance is greater than or equal to the second clock impedance based at least in part on the second impedance adjustment circuitry and the fourth impedance adjustment circuitry being connected in parallel.
4. The memory system of claim 1 , wherein the first controllable impedance is equivalent to the third controllable impedance, and the second controllable impedance is equivalent to the fourth controllable impedance.
5. The memory system of claim 1 , wherein the first controllable impedance differs from the third controllable impedance, and wherein the second controllable impedance differs from the fourth controllable impedance.
6. A method, comprising:
receiving a first clock signal having a first clock impedance at a first clock terminal of a first memory device and at a first clock terminal of a second memory device;
receiving a second clock signal having a second clock impedance at a second clock terminal of the first memory device and at a second clock terminal of the second memory device;
adjusting a first controllable impedance at the first clock terminal of the first memory device and a first controllable impedance at the first clock terminal of the second memory device to provide a first combined controllable impedance that is based at least in part on the first clock impedance; and
adjusting a second controllable impedance at the second clock terminal of the first memory device and a second controllable impedance at the second clock terminal of the second memory device to provide a second combined controllable impedance that is based at least in part on the second clock impedance.
7. The method of claim 6 , wherein:
the first controllable impedance at the first clock terminal of the first memory device and the first controllable impedance at the first clock terminal of the second memory device are greater than the first clock impedance, and
the second controllable impedance at the second clock terminal of the first memory device and the second controllable impedance at the second clock terminal of the second memory device are greater than the second clock impedance.
8. The method of claim 6 , wherein:
the first controllable impedance at the first clock terminal of the first memory device is equivalent to the first controllable impedance at the first clock terminal of the second memory device, and
the second controllable impedance at the second clock terminal of the first memory device is equivalent to the second controllable impedance at the second clock terminal of the second memory device.
9. The method of claim 6 , wherein:
the first controllable impedance at the first clock terminal of the first memory device differs from the first controllable impedance at the first clock terminal of the second memory device, and
the second controllable impedance at the second clock terminal of the first memory device differs from the second controllable impedance at the second clock terminal of the second memory device.
10. The method of claim 6 , wherein:
the first combined controllable impedance is greater than or equal to the first clock impedance based at least in part on the first clock terminal of the first memory device and the first clock terminal of the second memory device being connected in parallel, and
the second combined controllable impedance is greater than or equal to the second clock impedance based at least in part on the second clock terminal of the second memory device and the second clock terminal of the second memory device being connected in parallel.
11. The memory system of claim 1 , further comprising:
a first clock terminal coupled with the first impedance adjustment circuitry and configured to receive the first clock signal;
a second clock terminal coupled with the second impedance adjustment circuitry and configured to receive the second clock signal;
a third clock terminal coupled with the third impedance adjustment circuitry and configured to receive the first clock signal; and
a fourth clock terminal coupled with the fourth impedance adjustment circuitry and configured to receive the second clock signal.
12. The memory system of claim 1 , wherein:
the first impedance adjustment circuitry is associated with a first plurality of memory cells of the first memory device and the second impedance adjustment circuitry is associated with a second plurality of memory cells of the first memory device, and
the third impedance adjustment circuitry is associated with a third plurality of memory cells of the second memory device and the fourth impedance adjustment circuitry is associated with a fourth plurality of memory cells of the second memory device.
13. The memory system of claim 1 , wherein the first memory device and the second memory device are dynamic random access memory (DRAM) devices.
14. The method of claim 6 , wherein:
the first clock terminal of the first memory device is associated with a first plurality of memory cells of the first memory device and the second clock terminal of the first memory device is associated with a second plurality of memory cells of the first memory device, and the first clock terminal of the second memory device is associated with a first plurality of memory cells of the second memory device and the second clock terminal of the second memory device is associated with a second plurality of memory cells of the second memory device.
15. The method of claim 6 , wherein the first memory device and the second memory device are dynamic random access memory (DRAM) devices.