IP Library › Granted Patent US 12,381,518
Granted Patent B2
US 12,381,518 · App. 17/971,490 · Granted Aug 5, 2025

Low-noise amplifier (LNA) input impedance adjustment circuit

Inventors: Amjath Husain (Bangalore, IN); Girish Koppassery (Bangalore, IN); Madhukar Vallabhaneni (Bengaluru, IN)
Assignee: QUALCOMM Incorporated
H03F1/565H03F3/193H04B1/18H03F2200/294H03F2200/372H03F2200/451
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Quick Facts
Patent No.
US 12,381,518
App. No.
17/971,490
Granted
Aug 5, 2025
Kind
B2
Abstract

Aspects of the present disclosure provide a circuit configured to adjust an input impedance of an amplifier such as a low-noise amplifier. In certain aspects, the circuit is coupled to a node, wherein the node is between a first transistor and a second transistor of the amplifier. The circuit may include an inductor and a capacitor coupled in series, wherein the inductor is coupled with one or more load inductors of the amplifier through negative magnetic coupling.

Claims (32)

1. An apparatus, comprising:

an amplifier, comprising:

a first transistor having a gate, a source, and a drain, wherein the gate of the first transistor is coupled to an input of the amplifier, and the source of the first transistor is coupled to a ground;

a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor is configured to receive a bias voltage, and the source of the second transistor is coupled to the drain of the first transistor;

a first inductor coupled between the drain of the second transistor and a supply rail; and

a circuit coupled to a node, wherein the node is between the first transistor and the second transistor, and the circuit comprises:

a second inductor, wherein the second inductor is coupled with the first inductor through negative magnetic coupling; and

a capacitor coupled in series with the second inductor.

2. The apparatus of claim 1 , wherein the circuit is coupled between the node and the supply rail.

3. The apparatus of claim 1 , wherein the circuit is coupled between the node and the ground.

4. The apparatus of claim 1 , further comprising a filter coupled to the input of the amplifier.

5. The apparatus of claim 4 , wherein the filter comprises a bandpass filter.

6. The apparatus of claim 1 , wherein the amplifier further comprises a third inductor magnetically coupled with the first inductor.

7. The apparatus of claim 6 , wherein the third inductor is coupled to an output of the amplifier.

8. The apparatus of claim 7 , further comprising a mixer coupled to the output of the amplifier.

9. The apparatus of claim 1 , wherein the amplifier further comprises a source inductor coupled between the source of the first transistor and the ground.

10. The apparatus of claim 1 , wherein the amplifier further comprises a gate inductor coupled between the gate of the first transistor and the input of the amplifier.

11. The apparatus of claim 1 , wherein the capacitor comprises a variable capacitor.

12. The apparatus of claim 11 , wherein the variable capacitor comprises multiple switching-capacitor circuits coupled in parallel, each of the switching-capacitor circuits comprising a respective capacitor and a respective switch coupled in series.

13. The apparatus of claim 1 , wherein the first inductor is coupled to an output of the amplifier.

14. The apparatus of claim 13 , further comprising a mixer coupled to the output of the amplifier.

15. The apparatus of claim 1 , further comprising a radio frequency (RF) front-end module, wherein the RF front-end module includes:

the amplifier; and

a filter coupled to the input of the filter.

16. The apparatus of claim 15 , wherein the filter comprises a bandpass filter.

17. The apparatus of claim 15 , wherein the RF front-end module is coupled between an antenna and a receive circuit.

18. The apparatus of claim 17 , wherein the receive circuit is integrated on a chip coupled to the RF front-end module.

19. The apparatus of claim 1 , further comprising:

a second capacitor coupled to the first inductor; and

a resistor coupled to the first inductor.

20. The apparatus of claim 19 , wherein the second capacitor is coupled in parallel with the first inductor.

21. The apparatus of claim 19 , wherein the resistor is coupled in parallel with the first inductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2022
From: HUSAIN, AMJATH; KOPPASSERY, GIRISH; VALLABHANENI, MADHUKAR
To: QUALCOMM INCORPORATED
Reel/Frame 062086/0717 →
Continuity (2)
Provisional Application 63263124 · Oct 27, 2021
Related Publication 20230126116A1 · Apr 27, 2023
References Cited (8)
US 20170163215A1 · Gorbachov et al. · 2017 [cited by applicant]
US 20170237402A1 · Kim et al. · 2017 [cited by applicant]
Cassan D.J., et al., “A 1-V Transformer-Feedback Low-Noise Amplifier for 5-GHz Wireless LAN in 0.18-μm CMOS”, IEEE Journal of Solid-State Circuits, vol. 38, No. 3, DOI: 10.1109/JSSC.2002.808284, Mar. 2003, pp. 427-435. [cited by applicant]
Mineyama A., et al., “A Millimeter-Wave CMOS Low Noise Amplifier using Transformer Neutralization Techniques”, Asia-Pacific Microwave Conference 2011, 2011, pp. 223-226. [cited by applicant]
Gangopadhyay D., et al., “A 1.6 mW 5.4 GHz Transformer-Feedback gm-Boosted Current-Reuse LNA in 0.18μm CMOS”, IEEE International Symposium on Circuits and Systems, ISCAS 2010—May 30-Jun. 2, 2010—Paris, France, IEEE, US,… [cited by applicant]
International Search Report and Written Opinion—PCT/US2022/047598—ISA/EPO—Feb. 13, 2023. [cited by applicant]
Plessas F., et al., “A 5 GHZ Low Noise Amplifier on 0.35 μm BiCMOS SiGe”, Electronics, Circuits and Systems, ICECS 2003, Proceedings of the 2003 10th IEEE International Conference on, [Online], Jan. 1, 2003, pp. 1082-10… [cited by applicant]
Toofan S., et al., “Low Power and High Gain Current Reuse LNA with Modified Input Matching and Inter-Stage Inductors”, Microelectronics Journal, Mackintosh Publications LTD, Luton, GB, vol. 39, No. 12, Dec. 1, 2008, pp.… [cited by applicant]
Cited By (1)
US 12,712,574