Temperature sensor circuits for integrated circuit devices
An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
1. An integrated circuit device, comprising:
a temperature sensor circuit, the temperature sensor circuit including an insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure, each channel provides a controllable impedance path between a commonly connected source terminal and a commonly connected drain terminal; and
wherein the temperature sensor circuit provides at least one temperature signal, the at least one temperature signal indicates a temperature window in which the integrated circuit device is operating and the control gate structure operates as a control gate for commonly selecting between a high impedance state and a low impedance state for each of the controllable impedance paths.
2. The integrated circuit device of claim 1 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 10 nm.
3. The integrated circuit device of claim 1 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 6 nm.
4. The integrated circuit device of claim 1 , further including:
the temperature sensor circuit includes a reference generator circuit, the reference generator circuit includes the IGFET and provides a temperature dependent reference potential.
5. The integrated circuit device of claim 4 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 10 nm.
6. The integrated circuit device of claim 5 wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 6 nm.
7. The integrated circuit device of claim 5 , wherein:
the reference generator circuit provides an essentially temperature independent reference potential.
8. The integrated circuit device of claim 1 , further including:
a refresh control circuit coupled to receive the at least one temperature signal, the refresh control circuit sets a refresh rate in response to the at least one temperature signal wherein
the integrated circuit device is a dynamic random access memory device.
9. The integrated circuit device of claim 8 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 10 nm.
10. The integrated circuit device of claim 9 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 6 nm.
11. The integrated circuit device of claim 1 , further including:
an assist control circuit coupled to receive the at least one temperature signal, the assist control circuit enables and disables an assist circuit in response to the at least one temperature signal, the assist circuit assists a data transfer operation of static random access memory cells formed on the integrated circuit device.
12. The integrated circuit device of claim 11 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 10 nm.
13. The integrated circuit device of claim 12 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 6 nm.
14. The integrated circuit device of claim 12 , wherein:
the assist circuit assists a read operation of data from static random access memory cells formed on the integrated circuit device.
15. The integrated circuit device of claim 12 , wherein:
the assist circuit assists a write operation of data to static random access memory cells formed on the integrated circuit device.
16. The integrated circuit device of claim 1 , further including:
a frequency control circuit coupled to receive the at least one temperature signal, the frequency control circuit sets the frequency of a clock signal in response to the at least one temperature signal and the integrated circuit device includes processor circuitry coupled to receive the clock signal.
17. The integrated circuit device of claim 16 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 10 nm.
18. The integrated circuit device of claim 17 , wherein:
the insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure that has a gate length of less than about 6 nm.
19. The integrated circuit device of claim 1 , further including:
a power up circuit, the power up circuit provides a power up signal having a power up logic level in response to detecting power received by the integrated circuit device, the temperature sensor circuit coupled to receive the power up signal and provides a predetermined state to the at least one temperature signal in response to the power up signal.
20. The integrated circuit device of claim 1 , wherein:
the insulated gate field effect transistor (IGFET) including at least four substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure, the at least four substantially horizontally disposed channels are electrically connected to a common source region.