Integration of discrete embeddable capacitors on integrated circuit chips
Single-chip solutions and related methods that result in much higher capacitance densities than is achievable with current on-chip solutions and which reduce consumption of planar area of a mounting structure. Embodiments of the present invention use vertical stacking to affix one or more discrete embeddable capacitors to an IC chip superstructure or base structure, and either sequentially or concurrently form electrical connections between the discrete embeddable capacitors and the IC chip. The inventive processes are compatible with CMOS fabrication temperatures for the IC chip while allowing use of capacitors that are fabricated using other processes that may involve much higher temperatures. The inventive processes allow connection of relatively large capacitances (e.g., ˜0.5 μF-1 μF) to an IC chip without increasing the 2-D footprint of the IC chip. Some embodiments include reconfigurable discrete/affixed capacitors and/or discrete/affixed capacitors with through-vias (distinct from capacitor electrode connections) for connecting circuitry.
1 . An integrated circuit chip structure including an integrated circuit chip having a first surface and internal circuitry, and including at least one discrete embeddable capacitor affixed to the first surface and electrically coupled to the internal circuitry, wherein at least one of the at least one discrete embeddable capacitor is internally partitioned into an array of capacitor cells and wherein the internal circuitry of the integrated circuit chip includes at least one of a switch or a fuse coupled to at least two capacitor cells of the array of capacitor cells and configured to electrically connect the at least two capacitor cells.
2 . The integrated circuit chip structure of claim 1 , wherein at least one of the at least one discrete embeddable capacitor is a multi-layer ceramic capacitor.
3 . The integrated circuit chip structure of claim 1 , wherein at least one of the at least one discrete embeddable capacitor includes main electrodes and through-vias electrically isolated from the main electrodes.
4 . The integrated circuit chip structure of claim 1 , wherein at least one of the at least one discrete embeddable capacitor includes internal main electrodes.
5 . The integrated circuit chip structure of claim 4 , wherein at least one of the at least one discrete embeddable capacitor includes through-vias electrically isolated from the internal main electrodes.
6 . The integrated circuit chip structure of claim 1 , wherein at least one of the at least one discrete embeddable capacitor includes internal main electrodes and, coupled to the internal main electrodes, respective bonding pads suitable for forming hybrid bonds.
7 . The integrated circuit chip structure of claim 6 , wherein at least one of the at least one discrete embeddable capacitor includes through-vias electrically isolated from the internal main electrodes.
8 . The integrated circuit chip structure of claim 1 , wherein at least one of the at least one discrete embeddable capacitor includes external main electrodes.
9 . The integrated circuit chip structure of claim 8 , wherein at least one of the at least one discrete embeddable capacitor includes through-vias electrically isolated from the external main electrodes.
10 . The integrated circuit chip structure of claim 1 , wherein the at least one discrete embeddable capacitor is affixed to the first surface, and then electrically coupled to the internal circuitry.
11 . The integrated circuit chip structure of claim 10 , wherein the at least one discrete embeddable capacitor is electrically coupled to the internal circuitry through a redistribution layer.
12 . The integrated circuit chip structure of claim 10 , wherein the at least one discrete embeddable capacitor is individually affixed to the first surface.
13 . The integrated circuit chip structure of claim 12 , wherein the at least one discrete embeddable capacitor is electrically coupled to the internal circuitry through a redistribution layer.
14 . The integrated circuit chip structure of claim 10 , wherein the at least one discrete embeddable capacitor is concurrently affixed to the first surface by application to first surface of a reconstituted wafer bearing the at least one discrete embeddable capacitor.
15 . The integrated circuit chip structure of claim 14 , wherein the at least one discrete embeddable capacitor is electrically coupled to the internal circuitry through a redistribution layer.
16 . The integrated circuit chip structure of claim 1 , wherein the at least one discrete embeddable capacitor is concurrently affixed to the first surface and electrically coupled to the internal circuitry.
17 . The integrated circuit chip structure of claim 16 , wherein the at least one discrete embeddable capacitor is concurrently affixed to the first surface and electrically coupled to the internal circuitry by a hybrid bonding process.
18 . The integrated circuit chip structure of claim 16 , wherein the at least one discrete embeddable capacitor is concurrently affixed to the first surface and electrically coupled to the internal circuitry by a pillar bump process.
19 . The integrated circuit chip structure of claim 1 , wherein the at least one of a switch or a fuse is configured to connect the at least two capacitor cells in series.
20 . The integrated circuit chip structure of claim 1 , wherein the internal circuitry of the integrated circuit chip includes at least two switches and/or fuses electrically coupled to at least two capacitor cells of the array of capacitor cells and configured to connect the at least two capacitor cells in parallel.