Analog inverter based DC offset correction circuit
One aspect can provide a direct current (DC) feedback circuit. The DC feedback circuit can include a gain path, a first feedback capacitor coupled, in parallel, to the gain path, and an input resistor coupled to an input of the gain path and the first feedback capacitor. The gain path can include an input stage with a pair of transconductance amplifiers, a gain stage with one or more amplifiers, and an output stage with at least one negative feedback amplifier.
1 . A direct current (DC) feedback circuit, the circuit comprising:
a gain path;
a first feedback capacitor coupled, in parallel, to the gain path; and
an input resistor coupled to an input of the gain path and the first feedback capacitor, the gain path, the first feedback capacitor, and the input resistor forming a first Miller circuit that amplifies a capacitance of the first feedback capacitor;
wherein the gain path comprises an input stage with a pair of transconductance amplifiers, an adjustable gain stage comprising a plurality of cascaded amplifiers, and an output stage;
wherein the adjustable gain stage comprises a selector switch comprising a plurality of pass/transmission gates coupled to the plurality of cascaded amplifiers in the adjustable gain stage;
wherein the output stage comprises a second Miller circuit comprising a second feedback capacitor; and
wherein a capacitance of the second feedback capacitor is smaller than the capacitance of the first feedback capacitor.
2 . The DC feedback circuit of claim 1 , wherein a capacitance of the first feedback capacitor is between 10 pF and 50 pF.
3 . The DC feedback circuit of claim 2 , wherein a cutoff frequency of the DC feedback circuit is between 100 KHz and 1 MHz.
4 . The DC feedback circuit of claim 1 , wherein the pair of transconductance amplifiers are inverting amplifiers, and wherein a transconductance ratio between the pair of transconductance amplifiers is between one and five.
5 . The DC feedback circuit of claim 1 , wherein the second Miller circuit is to provide stability to the DC feedback circuit, and wherein the second Miller circuit further comprises an inverting amplifier and a resistor.
6 . The DC feedback circuit of claim 5 , wherein a resistance of the resistor in the second Miller circuit is smaller than a resistance of the input resistor in the first Miller circuit.
7 . The DC feedback circuit of claim 1 , wherein the first feedback capacitor is coupled to the gain path via a switch.
8 . The DC feedback circuit of claim 1 , wherein the amplifiers in the gain stage comprise inverting amplifiers, and wherein a total number of inverting amplifiers in the circuit is determined to ensure that the circuit provides a negative DC feedback.
9 . The DC feedback circuit of claim 1 , further comprising an inverter coupled to an output of the gain path and the first feedback capacitor.
10 . The DC feedback circuit of claim 1 , wherein the input resistor is coupled to an output of a to-be-compensated circuit, and wherein an output of the gain path is coupled to an input of the to-be-compensated circuit, thereby allowing the DC-feedback circuit to provide DC-offset compensation to the to-be-compensated circuit.
11 . The DC feedback circuit of claim 10 , wherein the to-be-compensated circuit is a frontend circuit of a high-speed receiver.
12 . A high-speed receiver frontend circuit, comprising:
a plurality of cascaded amplifier stages; and
a DC-offset-compensation circuit coupled to one or more cascaded amplifier stages to provide DC-offset compensation;
wherein the DC-offset-compensation circuit comprises:
a gain path;
a first feedback capacitor coupled, in parallel, to the gain path; and
an input resistor coupled to an input of the gain path and the first feedback capacitor, the gain path, the first feedback capacitor, and the input resistor forming a first Miller circuit that amplifies a capacitance of the first feedback capacitor;
wherein the gain path comprises an input stage with a pair of transconductance amplifiers, an adjustable gain stage comprising a plurality of cascaded amplifiers, and an output stage;
wherein the adjustable gain stage comprises a selector switch comprising a plurality of pass/transmission gates coupled to the plurality of cascaded amplifiers in the adjustable gain stage;
wherein the output stage comprises a second Miller circuit comprising a second feedback capacitor; and
wherein a capacitance of the second feedback capacitor is smaller than the capacitance of the first feedback capacitor.
13 . The receiver frontend circuit of claim 12 , wherein a capacitance of the first feedback capacitor is between 10 pF and 50 pF.
14 . The receiver frontend circuit of claim 12 , wherein the pair of transconductance amplifiers are inverting amplifiers, and wherein a transconductance ratio between the pair of transconductance amplifiers is between one and ten.
15 . The receiver frontend circuit of claim 12 , wherein the second Miller circuit is to provide stability to the DC-offset-compensation circuit, and wherein the second Miller circuit further comprises an inverting amplifier and a resistor.
16 . The receiver frontend circuit of claim 15 , wherein a resistance of the resistor in the second Miller circuit is smaller than a resistance of the input resistor in the first Miller circuit.
17 . The receiver frontend circuit of claim 12 , wherein the first feedback capacitor is coupled to the gain path via a switch.
18 . The receiver frontend circuit of claim 12 , wherein the amplifiers in the gain stage comprise one or more inverting amplifiers, and wherein a total number of inverting amplifiers in the circuit is determined to ensure that the DC-offset-compensation circuit provides a negative DC feedback to the coupled one or more cascaded amplifier stages.
19 . The receiver frontend circuit of claim 12 , wherein the DC-offset-compensation circuit further comprises an inverter coupled to an output of the gain path and the first feedback capacitor.