Wireless power transmitter for high fidelity communications and high power transfer
Wireless power transfer systems, disclosed, include one or more circuits to facilitate high power transfer at high frequencies. Such wireless power transfer systems include a damping circuit, configured to dampen a wireless power signal such that communications fidelity is upheld at high power. The damping circuit includes at least a damping transistor that is configured to receive, from the transmitter controller, a damping signal for switching the transistor to control damping during transmission of the wireless data signals. Utilizing such systems enables wireless power transfer at high frequency, such as 13.56 MHz, at voltages over 1 Watt, while maintaining fidelity of in-band communications associated with the higher power wireless power signal.
1. A power amplifier comprising:
at least one transistor including a gate and a drain, the at least one transistor configured to receive a driving signal at the gate and invert a direct current (DC) power signal to generate inverted alternating current (AC) signals at a frequency, the inverted AC signals including in-band communications signals; and
a damping circuit configured to dampen the inverted AC signals during output of the inverted AC signals, the damping circuit including a damping transistor that is configured to receive a damping signal for switching the damping transistor to control damping during output of the inverted AC signals when the in-band communications signals are transmitted, and
wherein the damping circuit is in electrical parallel with the drain of the at least one transistor.
2. The power amplifier of claim 1 , wherein the damping circuit further includes a damping resistor that is in electrical series with the damping transistor and is configured to dissipate at least some power from the inverted AC signals.
3. The power amplifier of claim 2 , wherein the damping resistor has a resistor value that is configured for decreasing a rise time in the inverted AC signals.
4. The power amplifier of claim 2 , wherein the damping resistor has a resistor value that is configured for decreasing a fall time in the inverted AC signals.
5. The power amplifier of claim 1 , wherein the damping circuit further includes a damping capacitor that is in electrical series with, at least, the damping transistor.
6. The power amplifier of claim 5 , wherein the damping capacitor is configured to ensure damping is performed 180 degrees out of phase from a phase of the inverted AC signals.
7. The power amplifier of claim 5 , wherein the damping capacitor is configured to reduce one or more of undershoot conditions in the inverted AC signals, overshoot conditions in the inverted AC signals, or combinations thereof.
8. The power amplifier of claim 1 , wherein the damping circuit further includes a diode that is in electrical series with, at least, the damping transistor.
9. The power amplifier of claim 8 , wherein the diode is configured to prevent power efficiency loss in the inverted AC signals when the damping circuit is not active.
10. The power amplifier of claim 9 , wherein the inverted AC signals have a half-wave, sine wave voltage.
11. The power amplifier of claim 10 , further comprising a choke inductor connected between the DC power signal and the at least one transistor.
12. The power amplifier of claim 1 , further comprising a filter circuit including, at least, a filter capacitor and a filter inductor, the filter circuit configured for optimization based on a filter quality factor.
13. The power amplifier of claim 12 , wherein the filter quality factor (γ FILTER ) is defined as
γ
FILTER
=
1
R
o
L
o
C
o
.
14. The power amplifier of claim 12 , wherein the filter circuit is configured to filter out electromagnetic interference (EMI) output by the power amplifier.
15. A damping circuit for a power amplifier, the power amplifier generating inverted alternating current (AC) signals and the damping circuit for damping the inverted AC signals during transmission, the inverted AC signals including in-band communications signals, the damping circuit comprising:
a damping transistor that is configured to receive a damping signal for switching the damping transistor to control damping during output of the AC signals when the in-band communications signals are transmitted;
a damping resistor that is in electrical series with the damping transistor and is configured to dissipate at least some power from the inverted AC signals;
a damping capacitor that is in electrical series with, at least, the damping transistor; and
a diode that is in electrical series with, at least, the damping transistor.
16. The damping circuit of claim 15 , wherein the damping resistor has a value that is configured for one or more of decreasing a rise time in the inverted AC signals, decreasing a fall time in the inverted AC signals, or combinations thereof.
17. The damping circuit of claim 15 , wherein the damping capacitor is configured for one or more of ensuring damping is performed 180 degrees out of phase from a phase of the inverted AC signals, reducing undershoot conditions in the inverted AC signals, reducing overshoot conditions in the inverted AC signals, or combinations thereof.
18. The damping circuit of claim 15 , wherein the diode is configured to prevent power efficiency loss in the inverted AC signals when the damping circuit is not active.
19. The damping circuit of claim 15 , wherein the inverted AC signals have a half-wave, sine wave voltage.
20. A circuit comprising:
at least one transistor including a gate and a drain, the at least one transistor configured to receive a driving signal at the gate and invert a direct current (DC) power signal to generate inverted alternating current (AC) signals at a frequency, the inverted AC signals including in-band communications signals;
a damping transistor that is configured to receive a damping signal for switching the damping transistor to control damping during output of the inverted AC signals when the in-band communications signals are transmitted, wherein the damping transistor is in electrical parallel with the drain of the at least one transistor;
a damping resistor that is in electrical series with the damping transistor and is configured to dissipate at least some power from the inverted AC signals;
a damping capacitor that is in electrical series with, at least, the damping transistor;
a diode that is in electrical series with, at least, the damping transistor; and
a filter circuit including, at least, a filter capacitor and a filter inductor, the filter circuit configured for optimization based on a filter quality factor.