IP Library › Granted Patent US 11,816,561
Granted Patent B2
US 11,816,561 · App. 17/977,774 · Granted Nov 14, 2023

Methods, systems, articles of manufacture and apparatus to map workloads

Inventors: Estelle Aflalo (Haifa, IL); Amit Bleiweiss (Yad Binyamin, IL); Mattias Marder (Haifa, IL); Eliran Zimmerman (Maalot, IL)
Assignee: Intel Corporation
G06N3/063G06F9/5011G06F9/5044G06F18/217G06N3/08
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Quick Facts
Patent No.
US 11,816,561
App. No.
17/977,774
Granted
Nov 14, 2023
Kind
B2
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to map workloads. An example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.

Claims (35)

1. A non-transitory machine readable storage medium comprising instructions to cause first processor circuitry to at least:

determine first layer performance metrics associated with a first layer of a neural network (NN) model based on execution with a first configuration of hardware circuitry;

determine second layer performance metrics associated with the first layer of the NN model based on execution with a second configuration of hardware circuitry;

compare the first layer performance metrics and the second layer performance metrics; and

assign the first layer of the NN model to execute on one of the first or second configurations of hardware circuitry based on the comparison of the first layer performance metrics and the second layer performance metrics.

2. The non-transitory computer readable storage medium as defined in claim 1 , wherein the instructions cause the first processor circuitry to instantiate a simulator to determine the first layer performance metrics and the second layer performance metrics.

3. The non-transitory computer readable storage medium as defined in claim 1 , wherein the instructions cause the first processor circuitry to identify the first configuration and the second configuration of hardware circuitry to execute the NN model, the NN model including layers.

4. The non-transitory computer readable storage medium as defined in claim 1 , wherein the instructions cause the first processor circuitry to generate a relative score between the first layer performance metrics and the second layer performance metrics.

5. The non-transitory computer readable storage medium as defined in claim 4 , wherein the instructions cause the first processor circuitry to generate an iteration decision based on the relative score.

6. The non-transitory computer readable storage medium as defined in claim 5 , wherein the instructions cause the first processor circuitry to stop evaluating the first layer based on a convergence indicator corresponding to the iteration decision.

7. The non-transitory computer readable storage medium as defined in claim 6 , wherein the instructions cause the first processor circuitry to evaluate a second layer of the NN model in response to the convergence indicator.

8. The non-transitory computer readable storage medium as defined in claim 1 , wherein the instructions cause the first processor circuitry to override compiler directives corresponding to the first layer based on the comparison.

9. An apparatus to improve resource utilization comprising:

memory;

machine readable instructions; and

processor circuitry to at least one of instantiate or execute the machine readable instructions to:

determine first layer performance metrics associated with a first layer of a neural network (NN) model based on execution with a first configuration of hardware circuitry;

determine second layer performance metrics associated with the first layer of the NN model based on execution with a second configuration of hardware circuitry;

compare the first layer performance metrics and the second layer performance metrics; and

assign the first layer of the NN model to execute on one of the first or second configurations of hardware circuitry based on the comparison of the first layer performance metrics and the second layer performance metrics.

10. The apparatus as defined in claim 9 , wherein the processor circuitry is to instantiate a simulator to determine the first layer performance metrics and the second layer performance metrics.

11. The apparatus as defined in claim 9 , wherein the processor circuitry is to identify the first configuration and the second configuration of hardware circuitry to execute the NN model, the NN model including layers.

12. The apparatus as defined in claim 9 , wherein the processor circuitry is to generate a relative score between the first layer performance metrics and the second layer performance metrics.

13. The apparatus as defined in claim 12 , wherein the processor circuitry is to generate an iteration decision based on the relative score.

14. The apparatus as defined in claim 13 , wherein the processor circuitry is to discontinue evaluating the first layer based on a convergence indicator corresponding to the iteration decision.

15. The apparatus as defined in claim 14 , wherein the processor circuitry is to evaluate a second layer of the NN model in response to the convergence indicator.

16. The apparatus as defined in claim 9 , wherein the processor circuitry is to override compiler directives corresponding to the first layer based on the comparison.

17. A method to optimize resource utilization comprising:

determining, by executing an instruction with processor circuitry, first layer performance metrics associated with a first layer of a neural network (NN) model based on execution with a first configuration of hardware circuitry;

determining, by executing an instruction with the processor circuitry, second layer performance metrics associated with the first layer of the NN model based on execution with a second configuration of hardware circuitry;

comparing, by executing an instruction with the processor circuitry, the first layer performance metrics and the second layer performance metrics; and

assigning, by executing an instruction with the processor circuitry, the first layer of the NN model to execute on one of the first or second configurations of hardware circuitry based on the comparison of the first layer performance metrics and the second layer performance metrics.

18. The method as defined in claim 17 , further including instantiating a simulator to determine the first layer performance metrics and the second layer performance metrics.

19. The method as defined in claim 17 , further including detecting the first configuration and the second configuration of hardware circuitry to execute the NN model, the NN model including layers.

20. The method as defined in claim 17 , further including generating a relative score between the first layer performance metrics and the second layer performance metrics.

Continuity (2)
Continuation 16541878 · Aug 15, 2019
Related Publication 20230111365A1 · Apr 13, 2023