Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
1. A method of forming a semiconductor structure comprising:
providing parallel adjacent gate structures on a substrate, the parallel adjacent gate structures comprising an outer gate structure and an inner gate structure, wherein each of the parallel adjacent gate structures comprises a metal gate and a dielectric gate cap;
providing conductive trenches on opposite sides of the inner gate structure;
providing a first oxide layer on the dielectric gate caps;
providing contact area elements in the first oxide layer, wherein:
each of the contact area elements contacts one of the conductive trenches; and
upper surfaces of the contact area elements are substantially co-planar with an upper surface of the first oxide layer,
etching exposed portions of the first oxide layer to expose the dielectric gate caps;
recessing the exposed dielectric gate caps; and
depositing a second oxide layer to form airgaps, wherein portions of the airgaps are disposed in regions where the dielectric gate caps were recessed.
2. The method of claim 1 , wherein the airgaps extend vertically to a level above a top surface of the conductive trenches.
3. The method of claim 1 , comprising:
before the etching and the recessing, providing a protective mask on the contact area elements and a portion of the first oxide layer above the inner gate structure.
4. The method of claim 3 , wherein the airgaps extend vertically to a level above a top surface of the conductive trenches.
5. The method of claim 1 , comprising:
providing an insulator layer adjacent to the outer gate structure; and
providing the first oxide layer on the insulator layer.
6. The method of claim 1 , comprising:
recessing the exposed dielectric gate caps to expose the underlying metal gates.
7. The method of claim 1 , wherein the outer gate structure is a first outer gate structure, the parallel adjacent gate structures comprise a second outer gate structure, and the method comprises:
providing the inner gate structure between the first and second outer gate structures.
8. The method of claim 7 , comprising:
depositing the second oxide layer to form airgaps in regions above the first outer gate structure, the second outer gate structure, and the internal gate structure, wherein each airgap comprises a portion disposed directly above one of the gate structures.
9. The method of claim 1 , wherein the dielectric gate caps comprise nitride.
10. The method of claim 1 , wherein the dielectric gate caps comprise SiN.
11. The method of claim 1 , wherein the metal gates comprise tungsten.
12. The method of claim 1 , wherein the metal gates comprise a metal cap.
13. The method of claim 12 , wherein the metal caps comprises cobalt.
14. The method of claim 12 , wherein the metal caps comprises ruthenium.
15. The method of claim 1 , wherein the metal gates and the contact area elements each comprise a metal cap.
16. The method of claim 1 , wherein the contact area elements comprise tungsten.
17. The method of claim 3 , wherein the outer gate structure is a first outer gate structure, the parallel adjacent gate structures comprise a second outer gate structure, and the method comprises:
providing the inner gate structure between the first and second outer gate structures.
18. The method of claim 17 , comprising:
depositing the second oxide layer to form airgaps in regions above the first outer gate structure and the second outer gate structure, wherein each airgap comprises a portion disposed directly above one of the gate structures.
19. The method of claim 1 , wherein the conductive trenches comprise a silicide.