IP Library Granted Patent US 12,476,359
Granted Patent B2
US 12,476,359 · App. 17/981,358 · Granted Nov 18, 2025

Phased array antenna with high impedance surface

Inventors: Jae Yeong Lee (Pohang-si, KR); Won Bin Hong (Pohang-si, KR)
Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
H01Q3/34H01Q1/48H01Q1/52H01Q9/0421H01Q9/045
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Quick Facts
Patent No.
US 12,476,359
App. No.
17/981,358
Granted
Nov 18, 2025
Kind
B2
Abstract

A phased array antenna with a high impedance surface according to an embodiment of the present disclosure is a phased array antenna with a high impedance surface including a plurality of unit elements, and each of the plurality of unit elements includes a substrate, a partial ground plane formed at least partially on the substrate, a planar inverted-L radiator disposed on the partial ground plane, and a via wall integrated in parallel on both edges of the partial ground plane, and a one-dimensional electromagnetic bandgap (EBG) structure is embedded in an edge of the planar radiator side of the partial ground plane.

Claims (21)

1 . A phased array antenna with a high impedance surface, the phased array antenna comprising:

a plurality of unit elements,

wherein each of the plurality of unit elements includes:

a substrate;

a partial ground plane formed at least partially on the substrate;

a planar inverted-L radiator disposed on the partial ground plane; and

a via wall integrated in parallel on both edges of the partial ground plane,

wherein a one-dimensional electromagnetic bandgap (EBG) structure is embedded in an edge of a planar radiator side of the partial ground plane,

wherein the phased array antenna has a structure in which a one-dimensional EBG structure and an inverted-L antenna unit element are integrated, and a mutual coupling path between the plurality of unit elements caused by a surface current flowing through a common ground plane is suppressed due to high impedance surface characteristics of the via wall, compared to a linearly arrayed phased array antenna without the via wall, and

wherein the phased array antenna further comprises:

a feeding network configured of a coplanar waveguide with ground (CPWG) transmission line including a plurality of island-shaped via walls serving as a high impedance surface for reducing leakage power; and

a power distribution circuit, the power distribution circuit including a tapered T-shaped power divider to facilitate impedance matching and low loss feeding despite a constraint of electrode manufacturing resolution of an FR-4 PCB process with a preset minimum line width.

2 . The phased array antenna according to claim 1 , wherein the plurality of unit elements are linearly arrayed within 0.39λ 0 , λ 0 being a wavelength in a free space.

3 . The phased array antenna according to claim 1 ,

wherein the one-dimensional EBG structure includes a plurality of periodic unit cells, and

the plurality of periodic unit cells are arrayed in a line at the edge of the planar radiator side of the partial ground plane.

4 . The phased array antenna according to claim 3 , wherein the plurality of periodic unit cells configured in the one-dimensional EBG structure includes a meander strip line utilizing a single-layer FR-4 PCB process.

5 . The phased array antenna according to claim 3 , wherein the one-dimensional EBG structure is configured to operate as a high impedance surface having a slower wave behavior to be able to exhibit quadratic reflection phase than an antenna without a one-dimensional EBG structure.

6 . The phased array antenna according to claim 3 , wherein the phased array antenna is configured to operate as a high impedance surface having a slower wave behavior than an antenna without a one-dimensional EBG structure in a horizontal direction of an edge of the one-dimensional EBG structure so that surface wave control is able to be performed.

7 . The phased array antenna according to claim 1 , comprising:

a high impedance surface instead of a Balun, the Balun being an auxiliary circuit, such that wide-angle beam steering is allowed in a broadband and spherical coverage characteristics are provided despite utilization of a single-layer FR-4 PCB process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2022
From: LEE, JAE YEONG; HONG, WON BIN
To: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
Reel/Frame 061899/0946 →
Priority Claims (2)
KR 10-2021-0159784 · Nov 18, 2021 · national
KR 10-2022-0012481 · Jan 27, 2022 · national
Continuity (1)
Related Publication 20230155288A1 · May 18, 2023
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