IP Library Granted Patent US 12,588,287
Granted Patent B2
US 12,588,287 · App. 17/985,957 · Granted Mar 24, 2026

Circuit substrate

Inventors: Tetsuo Morita (Tokyo, JP); Hiroyuki Kimura (Tokyo, JP); Makoto Shibusawa (Tokyo, JP); Hiroshi Tabatake (Tokyo, JP); Yasuhiro Ogawa (Tokyo, JP)
Assignee: Magnolia White Corporation
H10D86/60G02F1/13624H10D30/6755H10D86/423H10D86/441H10D86/481H10D86/80G02F1/136286G02F1/1368H10D30/6731H10D30/6745H10K59/1201H10K59/1213H10K59/1216
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Quick Facts
Patent No.
US 12,588,287
App. No.
17/985,957
Granted
Mar 24, 2026
Kind
B2
Abstract

Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode, a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film.

Claims (20)

1 . A circuit substrate comprising:

a first transistor comprising:

a first gate electrode;

a first insulating film over the first gate electrode;

an oxide semiconductor film over the first insulating film; and

a first metal and a second metal over the oxide semiconductor film, the first metal and the second metal being electrically connected to the oxide semiconductor film;

a second transistor comprising:

a semiconductor film including silicon;

a second insulating film over the semiconductor film and under the first gate electrode;

a second gate electrode over the second insulating film; and

a third metal and a fourth metal electrically connected to the semiconductor film; and

an interlayer film located over the first metal and the second metal,

wherein the interlayer film is sandwiched between the third metal and the second insulating film and between the fourth metal and the second insulating film, and

wherein a conductive layer is disposed under the second insulating film and overlaps the first gate electrode in a plane view.

2 . The circuit substrate according to claim 1 ,

wherein a capacitor is formed by the conductive layer, the first gate electrode, and the second insulating film.

3 . The circuit substrate according to claim 1 ,

wherein the conductive layer includes silicon.

4 . The circuit substrate according to claim 1 ,

wherein an area of the oxide semiconductor film is smaller than an area of the first gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071604/0061 →
Priority Claims (1)
JP 2016-074019 · Apr 1, 2016 · national
Continuity (4)
Continuation 16952455 · Nov 19, 2020
Continuation 16234838 · Dec 28, 2018
Continuation 15462971 · Mar 20, 2017
Related Publication 20230074191A1 · Mar 9, 2023
References Cited (1)
US 10319752B2 · Kao et al. · 2019 [cited by examiner]