Method for automating semiconductor design based on artificial intelligence

1. A method for automating a semiconductor design based on artificial intelligence, the method performed by a computing device including at least one processor, the method comprising:

receiving feature information and logical design information of a semiconductor element; and

training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information;

wherein the feature information includes:

size information including at least one of a width or a height of the semiconductor element, and

type information indicating whether the semiconductor element is a macro cell;

wherein the training of the neural network model includes:

converting Netlist information of a hypergraph structure included in the logical design information into an ordinary graph structure expressing a connection relationship of the semiconductor elements one to one,

performing an action of placing the semiconductor element in the canvas based on a state including the feature information and the logical design information through the neural network model,

estimating a reward for the action, and

performing reinforcement learning for the neural network model by returning the reward to the neural network model.

2. The method of claim 1 , wherein the feature information further includes:

numerical information indicating the number of other elements connected to the semiconductor element.

3. The method of claim 1 , wherein the logical design information includes:

index information regarding a placement order of the semiconductor element, and Netlist information indicating a connection relationship of the semiconductor elements.

4. The method of claim 1 , wherein the action of the placing the semiconductor element in the canvas includes:

an action of placing a mask in the canvas and placing the semiconductor element in one area of a canvas area in which the mask is not placed.

5. The method of claim 4 , wherein the mask includes:

a first mask corresponding to an area in which the semiconductor element is capable of deviating from the canvas, and

a second mask corresponding to an area overlapped with a semiconductor element already placed in the canvas.

6. The method of claim 1 , wherein the reward includes:

a length of a wire concatenating the semiconductor elements placed in the canvas through the action, and

a congestion of the semiconductor elements placed in the canvas through the action.

7. The method of claim 6 , wherein the reward is computed by a weighted sum of the length of the wire and the congestion.

8. The method of claim 6 , wherein the congestion is computed as a ratio of a second routing resource indicating a required resource for concatenating the semiconductor elements placed in the canvas by the wire to a first routing resource indicating a supplied resource in which the wire may be assigned for each area of the canvas.

9. The method of claim 1 , wherein the estimating of the reward for the action includes:

generating a complete graph representing a state in which all of the semiconductor elements placed in the canvas are concatenated to each other through the action,

converting the complete graph into a minimum spanning tree,

computing a routing resource for each of edges constituting the minimum spanning tree, and

cumulatively summing the routing resources for respective edges, and estimating a congestion included the reward based on a result value derived through the cumulative summing.

10. The method of claim 9 , wherein the computing of the routing resource for each of the edges constituting the minimum spanning tree includes:

computing the number of cases for concatenating the semiconductor elements by the wire in the canvas by considering the placement of the semiconductor elements corresponding to a node of an edge, and

computing the routing resource for each of the edges by calculating an expectation value for a form in which the wire is to be placed in the canvas by considering the number of cases.

11. The method of claim 10 , wherein the expectation value for the form in which the wire is to be placed in the canvas includes:

a first expectation value in which the wire is to be vertically placed in a grid cell of the canvas, and

a second expectation value in which the wire is to be horizontally placed in the grid cell of the canvas.

12. The method of claim 9 , wherein the estimating of the congestion included in the reward based on the result value derived through the cumulative summing includes:

estimating the congestion included in the reward by averaging values of upper N % among the result values derived through the cumulative summing,

wherein N is a natural number.

13. A method for automating a semiconductor design based on artificial intelligence, the method performed by a computing device including at least one processor, the method comprising:

receiving feature information and logical design information of a semiconductor element; and

placing semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information, by using a neural network model,

wherein the neural network model is a model trained through reinforcement learning based on a state including the feature information and the logical design information of the semiconductor element, an action of placing the semiconductor element in the canvas, and a reward for the action,

wherein the state includes Netlist information of an ordinary graph structure generated by converting the Netlist information of a hypergraph structure included in the logical design information into the ordinary graph structure expressing a connection relationship of the semiconductor elements one to one.

14. A computer program stored in a non-transitory computer-readable storage medium, wherein the computer program executes the following operations for automating a semiconductor design based on artificial intelligence when the computer program is executed by one or more processors, the operations comprising:

an operation of receiving feature information and logical design information of a semiconductor element; and

an operation of training a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information;

wherein the feature information includes:

size information including at least one of a width or a height of the semiconductor element, and

type information indicating whether the semiconductor element is a macro cell;

wherein the operation of training the neural network model includes:

an operation of converting Netlist information of a hypergraph structure included in the logical design information into an ordinary graph structure expressing a connection relationship of the semiconductor elements one to one,

an operation of performing an action of placing the semiconductor element in the canvas based on a state including the feature information and the logical design information through the neural network model,

an operation of estimating a reward for the action, and

an operation of performing reinforcement learning for the neural network model by returning the reward to the neural network model.

15. A computing device for automating a semiconductor design based on artificial intelligence, the device comprising:

a processor including at least one core;

a memory including program codes executable in the processor; and

a network unit receiving feature information and logical design information of a semiconductor element,

wherein the processor configured to train a neural network model to place semiconductor elements in a canvas in an order by a large size based on the feature information and the logical design information;

wherein the feature information includes:

size information including at least one of a width or a height of the semiconductor element, and

type information indicating whether the semiconductor element is a macro cell;

wherein the processor further configured to:

convert Netlist information of a hypergraph structure included in the logical design information into an ordinary graph structure expressing a connection relationship of the semiconductor elements one to one,

perform an action of placing the semiconductor element in the canvas based on a state including the feature information and the logical design information through the neural network model,

estimate a reward for the action, and

perform reinforcement learning for the neural network model by returning the reward to the neural network model.