TECHNIQUES FOR DATA MOVEMENT TO A CACHE IN A DISAGGREGATED DIE SYSTEM
Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.
1 . An apparatus comprising:
a first die arranged to be included in a multi-die system; and
circuitry to:
receive a request for ownership of a cache line for an input/output (I/O) agent of an I/O device to writeback data to the cache line for a core of a processor to obtain and process the writeback data, wherein the cache line is associated with a first cache resident on a second die of the multi-die system that also includes the core or is associated with a second cache resident on the first die; and
grant the request for ownership of the cache line based, at least in part, on a data traffic source type associated with the I/O agent, the granted request to cause the writeback data to be stored to a cache line address for the cache line.
2 . The apparatus of claim 1 , the first cache resident on the second die comprising a level 3 (L3) cache shared by the core with other cores of the processor.
3 . The apparatus of claim 1 , wherein the I/O agent and I/O device are resident on a third die of the multi-die system.
4 . The apparatus of claim 3 , wherein the circuitry is communicatively coupled to the I/O agent resident on the third die via a chip-to-chip interconnect network arranged to operate according to the Universal Chiplet Interconnect Express (UCIe) specification.
5 . The apparatus of claim 1 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the first cache resident on the second die.
6 . The apparatus of claim 5 , the information to indicate the request for ownership is to the first cache comprises a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with the cache line address to store the writeback data, wherein to grant the request for ownership of the cache line to the first cache is based on the data traffic source type and the CLOS ID.
7 . The apparatus of claim 1 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the second cache resident on the first die.
8 . The apparatus of claim 7 , the information to indicate the request for ownership is to the second cache comprises an absence of a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with a cache line address at the first cache, wherein to grant the request for ownership of the cache line to the second cache is based on the data traffic source type and the absence of the CLOS ID.
9 . The apparatus of claim 1 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP), the PCIe request TLP to include information in TLP processing hint (TPH) bits to indicate a dynamic or static selection of a data direct I/O (DDIO) mode to cause the writeback data to be stored to the cache line address for the cache line, the selected DDIO mode to include one of a dynamic allocation that includes granting the request for ownership of the cache line for either the first cache or for the second cache, a core cache allocation that includes granting the request for ownership of the cache line for only the first cache, or an I/O cache allocation that includes granting the request for ownership of the cache line for only the second cache.
10 . The apparatus of claim 1 , the data traffic source type associated with the I/O agent comprises an input output memory management unit (IOMMU), a Compute Express Link (CXL) type 1 or type 2 device, an accelerator, a network interface controller (NIC), or an infrastructure processing unit (IPU).
11 . A method comprising:
receiving, by circuitry at a first die of a multi-die system, a request for ownership of a cache line for an input/output (I/O) agent of an I/O device to writeback data to the cache line for a core of a processor to obtain and process the writeback data, wherein the cache line is associated with a first cache resident on a second die of the multi-die system that also includes the core or is associated with a second cache resident on the first die; and
granting the request for ownership of the cache line based, at least in part, on a data traffic source type associated with the I/O agent, the granted request to cause the writeback data to be stored to a cache line address for the cache line.
12 . The method of claim 11 , the first cache resident on the second die comprising a level 3 (L3) cache shared by the core with other cores of the processor.
13 . The method of claim 11 , wherein the I/O agent and I/O device are resident on a third die of the multi-die system and the circuitry at the first die is communicatively coupled to the I/O agent resident on the third die via a chip-to-chip interconnect network arranged to operate according to the Universal Chiplet Interconnect Express (UCIe) specification.
14 . The method of claim 11 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the first cache resident on the second die and to indicate a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with the cache line address to store the writeback data, wherein granting the request for ownership of the cache line to the first cache is based on the data traffic source type and the CLOS ID.
15 . The method of claim 11 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the second cache resident on the first die and to indicate an absence of a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with a cache line address at the first cache, wherein granting the request for ownership of the cache line to the second cache is based on the data traffic source type and the absence of the CLOS ID.
16 . The method of claim 11 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP), the PCIe request TLP to include information in TLP processing hint (TPH) bits to indicate a dynamic or static selection of a data direct I/O (DDIO) mode to cause the writeback data to be stored to the cache line address for the cache line, the selected DDIO mode to include one of a dynamic allocation that includes granting the request for ownership of the cache line for either the first cache or for the second cache, a core cache allocation that includes granting the request for ownership of the cache line for only the first cache, or an I/O cache allocation that includes granting the request for ownership of the cache line for only the second cache.
17 . At least one machine readable medium comprising a plurality of instructions that in response to being executed by circuitry at a first die of a multi-die system, cause the circuitry to:
receive a request for ownership of a cache line for an input/output (I/O) agent of an I/O device to writeback data to the cache line for a core of a processor to obtain and process the writeback data, wherein the cache line is associated with a first cache resident on a second die of the multi-die system that also includes the core or is associated with a second cache resident on the first die; and
grant the request for ownership of the cache line based, at least in part, on a data traffic source type associated with the I/O agent, the granted request to cause the writeback data to be stored to a cache line address for the cache line.
18 . The at least one machine readable medium of claim 17 , the first cache resident on the second die comprising a level 3 (L3) cache shared by the core with other cores of the processor.
19 . The at least one machine readable medium of claim 17 , wherein the I/O agent and I/O device are resident on a third die of the multi-die system and the circuitry at the first die is communicatively coupled to the I/O agent resident on the third die via a chip-to-chip interconnect network arranged to operate according to the Universal Chiplet Interconnect Express (UCIe) specification.
20 . The at least one machine readable medium of claim 17 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the first cache resident on the second die and to indicate a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with the cache line address to store the writeback data, wherein to grant the request for ownership of the cache line to the first cache is based on the data traffic source type and the CLOS ID.
21 . The at least one machine readable medium of claim 17 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the second cache resident on the first die and to indicate an absence of a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with a cache line address at the first cache, wherein to grant the request for ownership of the cache line to the second cache is based on the data traffic source type and the absence of the CLOS ID.
22 . The at least one machine readable medium of claim 17 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP), the PCIe request TLP to include information in TLP processing hint (TPH) bits to indicate a dynamic or static selection of a data direct I/O (DDIO) mode to cause the writeback data to be stored to the cache line address for the cache line, the selected DDIO mode to include one of a dynamic allocation that includes granting the request for ownership of the cache line for either the first cache or for the second cache, a core cache allocation that includes granting the request for ownership of the cache line for only the first cache, or an I/O cache allocation that includes granting the request for ownership of the cache line for only the second cache.
23 . A multi-die system comprising:
a first die arranged to have an input/output (I/O) agent of an I/O device resident on the first die;
a second die arranged to have a core of a processor and a first cache resident on the second die; and
a third die arranged to have circuitry and a second cache resident on the third die, the circuitry to:
receive a request for ownership of a cache line for the I/O agent to writeback data to the cache line for the core of the processor to obtain and process the writeback data, wherein the cache line is associated with the first cache or is associated with the second cache; and
grant the request for ownership of the cache line based, at least in part, on a data traffic source type associated with the I/O agent, the granted request to cause the writeback data to be stored to a cache line address for the cache line.
24 . The multi-die system of claim 23 , the first cache comprising a level 3 (L3) cache arranged to be shared by the core with other cores of the processor.
25 . The multi-die system of claim 23 , wherein the circuitry is arranged to be communicatively coupled to the I/O agent resident on the third die via a chip-to-chip interconnect network arranged to operate according to the Universal Chiplet Interconnect Express (UCIe) specification.
26 . The multi-die system of claim 23 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the first cache and to indicate a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with the cache line address to store the writeback data, wherein to grant the request for ownership of the cache line to the first cache is based on the data traffic source type and the CLOS ID.
27 . The multi-die system of claim 23 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP) request, the PCIe request TLP to include information to indicate the request for ownership is to the second cache and to indicate a class of service (CLOS) identifier (ID) for the first cache, the CLOS ID associated with a cache line address at the first cache, wherein to grant the request for ownership of the cache line to the second cache is based on the data traffic source type and the absence of the CLOS ID.
28 . The multi-die system of claim 23 , wherein the request for ownership is to be received via a PCI Express (PCIe) request transaction layer packet (TLP), the PCIe request TLP to include information in TLP processing hint (TPH) bits to indicate a dynamic or static selection of a data direct I/O (DDIO) mode to cause the writeback data to be stored to the cache line address for the cache line, the selected DDIO mode to include one of a dynamic allocation that includes granting the request for ownership of the cache line for either the first cache or for the second cache, a core cache allocation that includes granting the request for ownership of the cache line for only the first cache, or an I/O cache allocation that includes granting the request for ownership of the cache line for only the second cache.
29 . The multi-die system of claim 23 , the data traffic source type associated with the I/O agent comprises an input output memory management unit (IOMMU), a Compute Express Link (CXL) type 1 or type 2 device, an accelerator, a network interface controller (NIC), or an infrastructure processing unit (IPU).