Broadband on-chip nested-loop alternating current (AC)-coupling systems and methods
Various embodiments of the invention provide for an AC-coupling method and systems that utilize a nested loop circuit to generate a differential mode output that facilitates an offset compensation and a common mode output that facilitates DC-biasing of an active circuit. In embodiments, the nested loop circuit comprises a differential amplifier and a differential mode loop that generates a differential mode output and a common mode loop that uses a common mode voltage and a reference voltage to generate the common mode output.
1. A nested loop circuit comprising:
a common mode loop that, in a closed loop configuration, uses a common mode voltage and a reference voltage to generate a common mode output that facilitates DC biasing of an active circuit; and
a differential mode loop that generates a differential mode output that facilitates an offset compensation,
wherein the common mode output and the differential mode output are coupled to a high impedance converter circuit that provides a high impedance loading to an input of the active circuit.
2. A nested loop circuit comprising:
a common mode loop that, in a closed loop configuration, uses a common mode voltage and a reference voltage to generate a common mode output that facilitates DC biasing of an active circuit; and
a differential mode loop that generates a differential mode output that facilitates an offset compensation,
wherein the differential mode loop is nested in the common mode loop.
3. A broadband amplifier circuit comprising:
a differential amplifier;
nested loop circuit coupled to the differential amplifier, the nested loop circuit comprising:
a common mode loop that, in a closed loop configuration, uses a common mode voltage and a reference voltage to generate a common mode output that facilitates DC biasing of an active circuit; and
a differential mode loop that generates a differential mode output that facilitates an offset compensation; and
a high impedance converter circuit coupled to the nested loop circuit, the high impedance converter circuit provides a high impedance input to the differential amplifier.
4. The broadband amplifier circuit of claim 3 , wherein the differential amplifier is coupled to a distributed network of input capacitors.
5. The broadband amplifier circuit of claim 3 , wherein the high impedance converter circuit comprises a voltage controlled current source that is coupled in a single-ended circuit configuration.
6. The broadband amplifier circuit of claim 3 , wherein the common mode loop is nested in the differential mode loop.
7. The broadband amplifier circuit of claim 3 , wherein the differential mode loop is nested in the common mode loop.
8. The broadband amplifier circuit of claim 3 , wherein the differential amplifier is coupled to Mach-Zehnder modulator.
9. The broadband amplifier circuit of claim 3 , wherein the differential amplifier is driven by a digital-to-analog-converter.
10. An AC-coupling method comprising:
using a nested loop circuit to generate a differential mode output, which facilitates an offset compensation and a common mode output that facilitates DC biasing of an active circuit, the nested loop circuit being coupled to a differential amplifier and comprising:
a common mode loop that, in a closed loop configuration, uses a common mode voltage and a reference voltage to generate the common mode output; and
a differential mode loop that generates the differential mode output.
11. The AC-coupling method of claim 10 , further comprising a high impedance converter circuit coupled to the nested loop circuit, the high impedance converter circuit provides a high impedance loading to an input of the active circuit.
12. The AC-coupling method of claim 11 , wherein the differential amplifier is coupled to a distributed network of input capacitors to reduce an effect of a parasitic capacitance.
13. The AC-coupling method of claim 12 , wherein the distributed network of input capacitors is implemented as an integrated DC blocking capacitor circuit.
14. The AC-coupling method of claim 12 , wherein the distributed network of input capacitors is implemented on a chip and defines a low cut-off frequency.
15. The AC-coupling method of claim 14 , wherein the chip comprises a set of inductors that are disposed in close physical proximity to each other on an upper metal layer of the chip to reduce a stray capacitance.
16. The AC-coupling method of claim 15 , wherein one or more of the set of inductors are disposed between two capacitors in the distributed network of input capacitors.