Materials and methods for fabricating superconducting quantum integrated circuits
Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm 2 ; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.
1. A superconducting integrated circuit configured to operate at a cryogenic temperature, comprising:
a substrate;
a plurality of Josephson junctions patterned from a plurality of stacked superconducting layers and intervening insulating layers, over a surface of the substrate, configured to switch at the cryogenic temperature;
the at least one intervening insulating layer configured to galvanically isolate the plurality of superconducting layers at the cryogenic temperature;
a kinetic inductance layer formed under the plurality of stacked superconducting lavers and patterned as a set of meander inductors defining a current distribution network for supplying current to the plurality of Josephson junctions, the kinetic inductance layer having a higher unit inductance than the respective plurality of superconductive layers at the cryogenic temperature; and
a patterned resistive layer, configured as damping elements for the plurality of Josephson junctions.
2. A method of forming an integrated circuit on a substrate configured to operate at a cryogenic temperature, comprising:
forming and patterning a kinetic inductance layer over the substrate, patterned into a current distribution network;
depositing a plurality of superconducting, lavers and intervening insulating layers over the kinetic inductance layer; and
patterning the plurality of superconducting layers and intervening insulating layers into a plurality of Josephson junctions,
the kinetic inductance layer having a higher unit inductance than the respective plurality, of superconductive layers at the cryogenic temperature.
3. The method according to claim 2 , further comprising forming a resistive layer over the Josephson junctions, configured as a set of resistive elements to damp respective Josephson junctions, wherein the at least one insulating layer is planarized.
4. The method according to claim 2 , wherein the kinetic inductance layer has kinetic inductance of at least 5 pH/square and the cryogenic temperature is less than 100 mK.
5. The method according to claim 2 , wherein the plurality of superconducting layers comprise niobium, and at least one of the intervening insulating layers comprises silicon nitride.
6. The method according to claim 2 , wherein the current distribution network is patterned as a meander inductor.
7. The method according to claim 2 , further comprising interconnecting the Josephson junctions to form a controller for at least one qubit operating at the cryogenic temperature.
8. An integrated circuit system, comprising:
a substrate;
a kinetic inductance layer configured as a current distribution network comprising meander inductors, formed over the substrate;
a plurality of stacked superconducting layers and intervening insulating layers, patterned into a plurality of Josephson junctions, the plurality of Josephson junctions receiving current from the meander inductors of the current distribution network; and
a patterned resistive layer, configured as damping elements for the plurality of Josephson junctions.
9. The integrated circuit according to claim 8 , further comprising a resistive layer, configured as a set of resistive elements to damp respective Josephson junctions.
10. The integrated circuit according to claim 8 , further comprising a resistive layer which remains non-superconducting at a temperature below 0.5° K, configured as a set of resistive elements to damp respective Josephson junctions.
11. The integrated circuit according to claim 8 , wherein the kinetic inductance layer has kinetic inductance of at least 5 pH/square.
12. The integrated circuit according to claim 8 , wherein the integrated circuit is configured to operate at a cryogenic temperature less than 0.5° K.
13. The integrated circuit according to claim 8 , wherein the plurality of Josephson junctions are planarized.
14. The integrated circuit according to claim 8 , wherein the kinetic inductance layer is configured as a ground plane on a substrate beneath the plurality of stacked superconducting layers.
15. The integrated circuit according to claim 8 , wherein the plurality of Josephson junctions each have a critical current density of less than 100 μA/μm 2 .
16. The integrated circuit according to claim 8 , further comprising a PdAu resistive layer, configured as a set of resistive elements to damp respective Josephson junctions,
wherein the plurality of Josephson junctions are adapted to operate at a cryogenic temperature below 100 mK.
17. The integrated circuit according to claim 8 , wherein the plurality of stacked superconducting layers comprise niobium, and the at least one intervening insulating layer comprises silicon nitride.
18. The integrated circuit according to claim 8 , wherein the plurality of Josephson junctions are interconnected to form a controller for at least one qubit.
19. The integrated circuit according to claim 8 , wherein the plurality of Josephson junctions are diffused with deuterium.
20. The integrated circuit according to claim 8 , further comprising an indium hump bond configured to provide an electrical interface of the integrated circuit, and at least one Ti adhesion layer adjacent to the resistive layer, wherein the patterned resistive layer comprises PdAu.