Gate-all-around device with different channel semiconductor materials and method of forming the same

1. A device comprising:

first semiconductor layers disposed over a first area of a substrate, wherein the first semiconductor layers are separated from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate, wherein one of the first semiconductor layers has a top surface facing away from the substrate and positioned at a first height above the substrate;

second semiconductor layers disposed over a second area of the substrate, wherein the second semiconductor layers are separated from each other and are stacked up along the direction generally perpendicular to the top surface of the substrate, wherein the first semiconductor layers include a first semiconductor material, and the second semiconductor layers include a second semiconductor material different from the first semiconductor material, wherein one of the second semiconductor layers has a top surface facing away from the substrate and positioned at the first height above the substrate;

a first gate structure wrapping around each of the first semiconductor layers; and

a second gate structure wrapping around each of the second semiconductor layers.

2. The device of claim 1 , wherein the one of the first semiconductor layers is a topmost first semiconductor layer from the first semiconductor layers.

3. The device of claim 1 , wherein the one of the first semiconductor layers is a bottommost first semiconductor layer form the first semiconductor layers, and

wherein the one of the second semiconductor layers is a bottommost second semiconductor layer from the second semiconductor layers.

4. The device of claim 1 , wherein the first semiconductor material includes silicon and the second semiconductor material includes germanium.

5. The device of claim 1 , wherein the number of first semiconductor layers is equal to the number of second semiconductor layers.

6. The device of claim 1 , further comprising a sidewall spacer extending from the one of the first semiconductor layers to the first area of the substrate.

7. The device of claim 1 , further comprising:

a first source/drain feature interfacing with the one of the first semiconductor layers; and

a second source/drain feature interfacing with the one of the second semiconductor layers.

8. The device of claim 1 , wherein the first gate structure wrapping around each of the first semiconductor layers incudes a first high-k dielectric layer and a first conductive material layer, and

wherein the second gate structure wrapping around each of the second semiconductor layers incudes a second high-k dielectric layer and a second conductive material layer.

9. A device comprising:

first semiconductor layers disposed over a substrate, wherein the first semiconductor layers are separated from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate, wherein a topmost first semiconductor layer from the first semiconductor layers extends to a first height above the substrate;

second semiconductor layers disposed over the substrate, wherein the second semiconductor layers are separated from each other and are stacked up along the direction generally perpendicular to the top surface of the substrate, wherein a topmost second semiconductor layer from the second semiconductor layers extends to the first height above the substrate, the topmost second semiconductor layer having a different material composition than the topmost first semiconductor layer;

a first gate structure wrapping around each of the first semiconductor layers; and

a second gate structure wrapping around each of the second semiconductor layers.

10. The device of claim 9 , wherein all of the first semiconductor layers are formed of a first material composition, and

wherein all of the second semiconductor layers are formed of a second material composition that is different than the first material composition.

11. The device of claim 9 , wherein the topmost first semiconductor layer includes silicon and the second topmost semiconductor layer includes germanium.

12. The device of claim 9 , wherein the first semiconductor layers are part of a n-type transistor and the second semiconductor layer are part of a p-type transistor.

13. The device of claim 9 , wherein a first portion of the substrate directly under the first semiconductor layers extends to a second height, and

wherein a second portion of the substrate directly under the second semiconductor layers extends to the second height.

14. The device of claim 13 , further comprising:

a first sidewall spacer extending from the first portion of the substrate to a bottommost first semiconductor layer from the first semiconductor layers; and

a second sidewall spacer extending from the second portion of the substrate to a bottommost second semiconductor layer from the second semiconductor layers, and

wherein the bottommost first semiconductor layer extends to a second height above the substrate and the bottommost second semiconductor layer extends to the second height above the substrate.

15. A method comprising:

forming a first semiconductor layer over a first area and a second area of a substrate;

removing the first semiconductor layer from over the first area of the substrate;

forming a spacer feature on the substrate between the first and second areas of the substrate;

forming a first stack of semiconductor layers over the first area of the substrate and a second stack of semiconductor layers over the first semiconductor layer disposed over the second area of the substrate, wherein the first stack of the semiconductor layer and the second stack of semiconductor layers interface with the spacer feature after the forming of the first stack of semiconductor layers over the first area of the substrate and the second stack of semiconductor layers over the first semiconductor layer disposed over the second area of the substrate;

removing the spacer feature;

patterning the first stack of semiconductor layers; and

patterning the second stack of semiconductor layers.

16. The method of claim 15 , wherein the forming of the first stack of semiconductor layers over the first area of the substrate and the second stack of semiconductor layers over the first semiconductor layer disposed over the second area of the substrate includes alternately forming second semiconductor layers and third semiconductor layers over the first and second areas of the substrate.

17. The method of claim 16 , wherein the second semiconductor layers include a second semiconductor material and the third semiconductor layers include the first semiconductor material, the second semiconductor material being different from the first semiconductor material.

18. The method of claim 15 , wherein the first area of the substrate is exposed after the removing of the first semiconductor layer from over the first area of the substrate.

19. The method of claim 15 , further comprising forming a buffer layer over the first stack of semiconductor layers, the second stack of semiconductor layers and the spacer feature prior to patterning the first stack of semiconductor layers and patterning the second stack of semiconductor layers.

20. The method of claim 19 , further comprising removing the buffer layer to expose a top surface of the spacer feature prior to the removing of the spacer feature.