Classification of different types of cache misses
Various examples are provided related to cache miss classification. In one example, a method for classification of cache misses includes detecting a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based coarse grain sampling; collecting a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and classifying a type of cache miss associated with the susceptible instruction. The type of cache miss can be classified as a capacity miss, a conflict miss, or a coherence miss using the memory access pattern of the susceptible instruction.
1 . A method for classification of cache misses, comprising:
detecting, by a computing device, a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based course coarse grain sampling;
collecting, by the computing device, a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and
classifying, by the computing device, a type of cache miss associated with the susceptible instruction, where the type of cache miss is classified as a capacity miss, a conflict miss, or a coherence miss based at least in part upon the memory access pattern of the susceptible instruction.
2 . The method of claim 1 , wherein the coarse grain sampling comprises filtering out sparse cache misses.
3 . The method of claim 2 , wherein the sparse cache misses are filtered out based upon comparison of a miss ratio for loads and stores within a sampling window to a predefined threshold.
4 . The method of claim 3 , wherein load and store memory accesses are stored separately in instruction stores.
5 . The method of claim 1 , wherein the breakpoint-based fine-grain sampling comprises collecting fine-grained memory accesses for the susceptible instruction in response to an installed breakpoint.
6 . The method of claim 1 , wherein the type of cache miss is classified as the capacity miss or the conflict miss based at least in part upon a number of cache misses and the memory access pattern.
7 . The method of claim 6 , comprising identifying, by the computing device, cache misses associated with a memory allocator from cache misses associated with an application.
8 . The method of claim 1 , wherein the type of cache miss is classified as the coherence miss based at least in part upon a number of misses on a cache line and cache set.
9 . The method of claim 8 , wherein word-level access information of the cache line is utilized to differentiate false sharing from true sharing.
10 . The method of claim 1 , further comprising modifying the program based upon the type of cache miss associated with the susceptible instruction.
11 . A system for classification of cache misses, comprising:
at least one computing device comprising processing circuitry, the at least one computing device configured to at least:
detect a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based coarse grain sampling;
collect a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and
classify a type of cache miss associated with the susceptible instruction, where the type of cache miss is classified as a capacity miss, a conflict miss, or a coherence miss based at least in part upon the memory access pattern of the susceptible instruction.
12 . The system of claim 11 , wherein the breakpoint-based fine-grain sampling comprises collecting fine-grained memory accesses for the susceptible instruction in response to an installed breakpoint.
13 . The system of claim 11 , wherein the type of cache miss is classified as the capacity miss or the conflict miss based at least in part upon a number of cache misses and the memory access pattern.
14 . The system of claim 13 , wherein the at least one computing device is further configured to identify cache misses associated with a memory allocator from cache misses associated with an application.
15 . The system of claim 11 , wherein the type of cache miss is classified as the coherence miss based at least in part upon a number of misses on a cache line and cache set.
16 . The system of claim 15 , wherein word-level access information of the cache line is utilized to differentiate false sharing from true sharing.
17 . The system of claim 11 , wherein the coarse grain sampling comprises filtering out sparse cache misses.
18 . The system of claim 11 , further comprising modifying the program based upon the type of cache miss associated with the susceptible instruction.
19 . A non-transitory computer-readable medium embodying a program executable in at least one computing device, where when executed the program causes the at least computing device to at least:
detect a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based coarse grain sampling;
collect a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and
classify a type of cache miss associated with the susceptible instruction, where the type of cache miss is classified as a capacity miss, a conflict miss, or a coherence miss based at least in part upon the memory access pattern of the susceptible instruction.
20 . The non-transitory computer-readable medium of claim 19 , wherein the program, when executed, causes the at least computing device to modify the program based upon the type of cache miss associated with the susceptible instruction.