Self-forming barrier for use in air gap formation
An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.
1 . A method of forming a semiconductor device, comprising:
providing parallel interconnects disposed in a dielectric material, wherein each of the parallel interconnects comprises:
a manganese doped copper interconnect material disposed in a liner; and
a conductive cap disposed on the manganese doped copper interconnect material;
depositing one or more additional layers on the dielectric material and exposed surfaces of the conductive caps;
subsequent to depositing the one or more additional layers, applying a thermal treatment to the parallel interconnects, wherein the thermal treatment forms a layer comprising:
manganese between the liner and the dielectric material; and
manganese between the conductive cap and the one or more additional layers;
patterning a lithography stack to form:
a first region where a first portion of the dielectric material is exposed; and
a second region where a second portion of the dielectric material is covered; and
etching the first portion of the dielectric material between the parallel interconnects in the first region.
2 . The method of claim 1 , comprising:
subsequent to the etching, depositing one or more capping layers to form airgaps between the parallel interconnects.
3 . The method of claim 2 , wherein the one or more capping layers comprise a non-conformally deposited dielectric material disposed above the parallel interconnects.
4 . The method of claim 3 , wherein the one or more capping layers comprise a conformally deposited capping material on exposed portions of the liner in the first region.
5 . The method of claim 1 , wherein the one or more additional layers comprise a hard mask layer.
6 . The method of claim 1 , wherein the patterning comprises: removing the one or more additional layers to expose the first portion of the dielectric material in the first region.
7 . The method of claim 1 , comprising: prior to the etching, damaging the first region of the dielectric material.
8 . The method of claim 7 , wherein damaging the first region comprises: exposing the first portion of the dielectric material to a chemical or plasma.
9 . The method of claim 1 , wherein the thermal treatment comprises annealing.
10 . The method of claim 1 , wherein the liner comprises tantalum (Ta).
11 . The method of claim 1 , wherein the liner comprises cobalt (Co).
12 . The method of claim 1 , wherein the liner comprises ruthenium (Ru).
13 . The method of claim 1 , wherein the liner comprises tantalum (Ta) and ruthenium (Ru).
14 . The method of claim 1 , wherein the liner comprises tantalum (Ta) and cobalt (Co).
15 . The method of claim 1 , wherein the liner comprises ruthenium (Ru) and cobalt (Co).
16 . The method of claim 1 , wherein the liner comprises tantalum (Ta), ruthenium (Ru), and cobalt (Co).
17 . The method of claim 1 , wherein the conductive cap comprises cobalt (Co).
18 . The method of claim 1 , wherein the conductive cap comprises ruthenium (Ru).
19 . The method of claim 1 , wherein the conductive cap comprises tantalum (Ta).