Insulated gate semiconductor device
An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type; a base contact region of the second conductivity-type; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and a high-concentration region of the first conductivity-type provided inside the carrier transport layer to be in contact with a part of a bottom surface of the lower buried region.
1 . An insulated gate semiconductor device comprising:
a carrier transport layer of a first conductivity-type;
an injection control region of a second conductivity-type on a top surface of the carrier transport layer;
a carrier supply region of the first conductivity-type selectively at an upper part of the injection control region;
a base contact region of the second conductivity-type selectively at an upper part of the injection control region;
a plurality of trenches penetrating the injection control region to reach the carrier transport layer;
an insulated gate structure inside the respective trenches of the plurality of trenches;
an upper buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the injection control region;
a lower buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and
a high-concentration region of the first conductivity-type inside the carrier transport layer, and in contact with a part of a bottom surface of the lower buried region between adjacent trenches of the plurality of trenches, the high-concentration region having a higher impurity concentration than the carrier transport layer and a width less than a width of the base contact region.
2 . The insulated gate semiconductor device of claim 1 , wherein the width of the high-concentration region is narrower than a gap between the adjacent trenches.
3 . The insulated gate semiconductor device of claim 1 , wherein the base contact region is in a middle between the adjacent trenches.
4 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the base contact region are separated from the adjacent trenches.
5 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the upper buried region are separated from the adjacent trenches.
6 . The insulated gate semiconductor device of claim 1 , wherein the upper buried region has a narrower width than the base contact region.
7 . The insulated gate semiconductor device of claim 1 , wherein the base contact region, the injection control region, the upper buried region, the lower buried region, and the high-concentration region straightly overlap with each other in a depth direction of the plurality of trenches.
8 . The insulated gate semiconductor device of claim 1 , wherein the carrier transport layer includes:
a drift layer of the first conductivity-type, and
a current spreading layer of the first conductivity-type on the drift layer.
9 . The insulated gate semiconductor device of claim 1 , wherein:
the adjacent trenches extend in a first direction parallel to each other in a planar pattern, and
the lower buried region includes:
stripe parts extending in the first direction, and
connecting parts connecting the stripe parts adjacent to each other in a second direction perpendicular to the first direction.
10 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the base contact region are in contact with the respective trenches adjacent to each other.
11 . The insulated gate semiconductor device of claim 1 , wherein the base contact region and the upper buried region are at positions shifted from each other in a depth direction of the plurality of trenches.
12 . The insulated gate semiconductor device of claim 1 , wherein the base contact region and the upper buried region are each in contact with only one trench of the adjacent trenches.
13 . The insulated gate semiconductor device of claim 1 , wherein
the adjacent trenches extend in a first direction parallel to each other in a planar pattern; and
the upper buried region has a stripe-shaped planar pattern extending in the first direction.
14 . The insulated gate semiconductor device of claim 13 , wherein the base contact region has a stripe-shaped planar pattern extending in the first direction.
15 . The insulated gate semiconductor device of claim 1 , wherein the high-concentration region is arranged intermittently in a direction in which the plurality of trenches extend in a planar pattern.
16 . The insulated gate semiconductor device of claim 1 , wherein the high-concentration region has a stripe-shaped planar pattern extending in a direction in which the plurality of trenches extend.
17 . The insulated gate semiconductor device of claim 1 , wherein the width of the high-concentration region is equal to a gap between the adjacent trenches.
18 . An insulated gate semiconductor device comprising:
a carrier transport layer of a first conductivity-type;
an injection control region of a second conductivity-type on a top surface of the carrier transport layer;
a carrier supply region of the first conductivity-type selectively at an upper part of the injection control region;
a base contact region of the second conductivity-type selectively at an upper part of the injection control region;
a plurality of trenches penetrating the injection control region to reach the carrier transport layer;
an insulated gate structure inside respective trenches of the plurality of trenches;
an upper buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the injection control region, the upper buried region having side surfaces on both sides of the upper buried region that are in contact with adjacent trenches of the plurality of trenches;
a lower buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and
a high-concentration region of the first conductivity-type inside the carrier transport layer, and in contact with a part of a bottom surface of the lower buried region between the adjacent trenches of the plurality of trenches, the high-concentration region having a higher impurity concentration than the carrier transport layer.
19 . An insulated gate semiconductor device comprising:
a carrier transport layer of a first conductivity-type;
an injection control region of a second conductivity-type on a top surface of the carrier transport layer;
a carrier supply region of the first conductivity-type selectively at an upper part of the injection control region;
a base contact region of the second conductivity-type selectively at an upper part of the injection control region;
a plurality of trenches penetrating the injection control region to reach the carrier transport layer;
an insulated gate structure inside respective trenches of the plurality of trenches;
an upper buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the injection control region;
a lower buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and
a high-concentration region of the first conductivity-type inside the carrier transport layer, and in contact with a part of a bottom surface of the lower buried region between adjacent trenches of the plurality of trenches, the high-concentration region having a higher impurity concentration than the carrier transport layer, wherein
the adjacent trenches extend in a first direction parallel to each other in a planar pattern,
the base contact region and the upper buried region are located at positions overlapping with each other intermittently in the first direction, and
a gap between the positions at which the base contact region and the upper buried region are located differs among a plurality of active areas.
20 . An insulated gate semiconductor device comprising:
a carrier transport layer of a first conductivity-type;
an injection control region of a second conductivity-type on a top surface of the carrier transport layer;
a carrier supply region of the first conductivity-type selectively at an upper part of the injection control region;
a base contact region of the second conductivity-type selectively at an upper part of the injection control region;
a plurality of trenches penetrating the injection control region to reach the carrier transport layer;
an insulated gate structure inside respective trenches of the plurality of trenches;
an upper buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the injection control region;
a lower buried region of the second conductivity-type inside the carrier transport layer and in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and
a high-concentration region of the first conductivity-type inside the carrier transport layer, and in contact with a part of a bottom surface of the lower buried region between adjacent trenches of the plurality of trenches, the high-concentration region having a higher impurity concentration than the carrier transport layer and a width greater than a width of the base contact region.