Translation table address storage circuitry
An apparatus has address translation circuitry to translate a target virtual address (VA) specified by a memory access request into a target physical address, first/second translation table address storage circuitry to store first/second translation table addresses; and protected region defining data storage circuitry to store region defining data specifying at least one protected region of virtual address space. In response to the memory access request: when the target VA is in the protected region(s), the address translation circuitry translates the target VA based on address translation data from a first translation table structure identified by the first translation table address. When the target VA is outside the protected region(s), the target VA is translated based on address translation data from a second translation table structure identified by the second translation table address.
1 . An apparatus comprising:
address translation circuitry configured to translate a target virtual address specified by a memory access request into a target physical address;
first translation table address storage circuitry configured to store a first translation table address;
second translation table address storage circuitry configured to store a second translation table address; and
protected region defining data storage circuitry configured to store region defining data specifying at least one protected region of virtual address space; in which:
in response to the memory access request, the address translation circuitry is configured to:
in response to the target virtual address being in the at least one protected region of virtual address space, translate the target virtual address based on address translation data from a first translation table structure identified by the first translation table address stored in the first translation table address storage circuitry; and
in response to the target virtual address being outside the at least one protected region of virtual address space, translate the target virtual address based on address translation data from a second translation table structure identified by the second translation table address stored in the second translation table address storage circuitry.
2 . The apparatus according to claim 1 , comprising at least one translation lookaside buffer configured to cache information derived from address translation data from one or more translation table structures; in which:
in response to a memory access request which misses in the at least one translation lookaside buffer, the address translation circuitry is configured to:
determine whether the target virtual address of the memory access request is in the at least one protected region of virtual address space specified by the region defining data; and
perform a page table walk operation using:
the first translation table address stored in the first translation table address storage circuitry when the target virtual address is in the at least one protected region; and
the second translation table address stored in the second translation table address storage circuitry when the target virtual address is outside the at least one protected region.
3 . The apparatus according to claim 1 , comprising processing circuitry configured to perform data processing in one of a plurality of domains of operation, in which:
when the processing circuitry is in a first domain, the address translation circuitry is configured to translate the target virtual address using address translation data from one of the first translation table structure and the second translation table structure depending on whether the target virtual address is in the at least one protected region.
4 . The apparatus according to claim 3 , in which when the processing circuitry is in a second domain, the address translation circuitry is configured to translate the target virtual address based on address translation data from a translation table structure identified by a translation table address obtained from a storage location selected independent of a determination of whether the target virtual address is in or outside the at least one protected region.
5 . The apparatus according to claim 4 , in which when the processing circuitry is in the second domain, the address translation circuitry is configured to obtain the translation table address from the second translation table address storage circuitry.
6 . The apparatus according to claim 4 , comprising further translation table address storage circuitry to store a further translation table address; in which:
when the processing circuitry is in the second domain, the address translation circuitry is configured to obtain the translation table address from the further translation table address storage circuitry.
7 . The apparatus according to claim 3 , comprising exception handling circuitry configured to control handling of exceptions; in which:
for at least one type of exception occurring for processing in the first domain, in response to an exception of said at least one type associated with a given virtual address, the exception handling circuitry is configured to:
perform a first exception handling action, when the given virtual address is in the at least one protected region; and
perform a second exception handling action different from the first exception handling action, when the given virtual address is outside the at least one protected region.
8 . The apparatus according to claim 7 , in which the first exception handling action comprises setting syndrome information to indicate that the exception is associated with a virtual address in the at least one protected region; and
the second exception handling action comprises setting the syndrome information to indicate that the exception is associated with a virtual address outside the at least one protected region.
9 . The apparatus according to claim 7 , in which the first exception handling action comprises triggering handling of the exception in the first domain; and
the second exception handling action comprises triggering handling of the exception in a second domain.
10 . The apparatus according to claim 3 , comprising at least one translation lookaside buffer comprising buffer entries to cache information derived from address translation data from one or more translation table structures, each buffer entry associated with a domain identifier identifying a corresponding one of the plurality of domains; in which:
in response to a translation invalidation command issued when the processing circuitry is in a second domain, the at least one translation lookaside buffer is configured to:
invalidate buffer entries for which at least one invalidation criterion specified by the translation invalidation command is satisfied and the domain identifier identifies the first domain, and
invalidate buffer entries for which the at least one invalidation criterion is satisfied and the domain identifier identifies the second domain.
11 . The apparatus according to claim 3 , in which the address translation circuitry is configured to translate the target virtual address to the target physical address in one of a plurality of physical address spaces selected based at least on a current domain of the processing circuitry.
12 . The apparatus according to claim 11 , in which the plurality of physical address spaces comprise at least a first physical address space associated with the first domain and a second physical address space associated with a second domain;
the first physical address space is accessible from the first domain and inaccessible from the second domain; and
the second physical address space is accessible from both the first domain and the second domain.
13 . The apparatus according to claim 12 , in which the plurality of physical address spaces also comprise a third physical address space associated with a third domain; and
the third physical address space is accessible from the third domain and inaccessible from the first domain and the second domain.
14 . The apparatus according to claim 12 , in which when the processing circuitry is in the third domain, the address translation circuitry is configured to translate the target virtual address based on address translation data from a translation table structure identified by a translation table address obtained from a storage location selected independent of a determination of whether the target virtual address is in or outside the at least one protected region.
15 . The apparatus according to claim 14 , comprising third translation table address storage circuitry configured to store a third translation table address; in which:
when the processing circuitry is in the third domain, the address translation circuitry is configured to obtain the translation table address from the third translation table address storage circuitry.
16 . The apparatus according to claim 1 , in which, for each protected region of said at least one protected region, the region defining data specifies a base address of the protected address region and a size of the protected address region.
17 . The apparatus according to claim 1 , in which the address translation circuitry is configured to perform a two-stage address translation based on a first-stage translation table structure specifying mapping from the target virtual address to a target intermediate address and a second-stage translation table structure specifying mapping from the target intermediate address to the target physical address;
the address translation circuitry is configured to obtain a first-stage translation table address identifying the first-stage translation table structure from one of the first translation table address storage circuitry and the second translation table address storage circuitry selected based on a determination of whether the target virtual address is in or outside the at least one protected region; and
the address translation circuitry is configured to obtain a second-stage translation table address identifying the second-stage translation table structure from one of first second-stage translation table address storage circuitry and second second-stage translation table address storage circuitry selected based on a determination of whether the target virtual address is in or outside the at least one protected region.
18 . A non-transitory computer-readable storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of target code; the computer program comprising:
address translation program logic to translate a target virtual address specified by a memory access request into a target physical address; and
state emulating logic to maintain state information emulating architectural state of a target instruction set architecture associated with the target code, the state information specifying:
a first translation table address;
a second translation table address; and
region defining data specifying at least one protected region of simulated virtual address space; in which:
in response to a memory access instruction of the target code, the address translation program logic is configured to:
in response to the target virtual address being in the at least one protected region of simulated virtual address space, translate the target virtual address based on address translation data from a first translation table structure identified by the first translation table address; and
in response to the target virtual address being outside the at least one protected region of simulated virtual address space, translate the target virtual address based on address translation data from a second translation table structure identified by the second translation table address.