IP Library Granted Patent US 12,696,510
Granted Patent B2
US 12,696,510 · App. 18/007,063 · Granted Jul 28, 2026

Enhancement-mode GaN HFET including ScAIN and method of manufacturing the same

Inventors: Jinqiao Xie (Allen, TX); Edward A. Beam, III (Plano, TX)
Assignee: Qorvo US, Inc.
H10D62/8503H10D30/015H10D30/475H10D62/824
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Quick Facts
Patent No.
US 12,696,510
App. No.
18/007,063
Filed
Jan 27, 2023
Granted
Jul 28, 2026
Kind
B2
Art Unit
2812
USPC
257/76
Abstract

A semiconductor device is disclosed. The semiconductor device has a substrate with a gallium nitride layer ( 14 ) disposed over the substrate. A scandium aluminum nitride layer ( 10 ) is disposed over the gallium nitride layer. A source ( 18 ) is in contact with the gallium nitride layer, and a drain ( 20 ) is spaced from the source, wherein the drain is in contact with the gallium nitride layer.

Claims (32)

1 . A semiconductor device comprising:

a substrate;

a gallium nitride layer disposed over the substrate;

an aluminum gallium nitride layer disposed over the gallium nitride layer, wherein the aluminum gallium nitride layer provides a wet etch stop once a surface of the aluminum gallium nitride layer is exposed to extend a gate recess through a scandium aluminum nitride layer disposed over the aluminum gallium nitride layer;

a source in contact with the gallium nitride layer;

a drain spaced from the source, wherein the drain is in contact with the gallium nitride layer; and

a gate that extends through the scandium aluminum nitride layer and is in contact with a surface of the aluminum gallium nitride layer to configure the semiconductor device for enhancement mode operation.

2 . The semiconductor device of claim 1 wherein the semiconductor device is a field-effect transistor having the enhancement mode of operation.

3 . The semiconductor device of claim 1 wherein the scandium aluminum nitride layer is between 20 Å and 500 Å thick.

4 . The semiconductor device of claim 1 further comprising a hard mask disposed over the scandium aluminum nitride layer.

5 . The semiconductor device of claim 4 wherein the hard mask is a silicon nitride layer.

6 . The semiconductor device of claim 1 wherein the scandium aluminum nitride layer is made of Sc x Al (1-x) N with x being between 0.1 and 0.3.

7 . The semiconductor device of claim 1 wherein the aluminum gallium nitride layer is made of Al y Ga (1-y) N with y being between 0.05 and 0.4.

8 . The semiconductor device of claim 4 wherein the hard mask is made of silicon oxide.

9 . A method of fabricating a semiconductor device comprising:

providing a substrate with a gallium nitride layer disposed over the substrate, an aluminum gallium nitride layer disposed over the gallium nitride layer, and a scandium aluminum nitride layer disposed over the aluminum gallium nitride layer,

disposing a hard mask over the scandium aluminum nitride layer;

forming a source in contact with the gallium nitride layer;

forming a drain spaced from the source, wherein the drain is in contact with the gallium nitride layer;

dry etching a gate recess through the hard mask; and

wet etching through the scandium aluminum nitride layer until the wet etching inherently stops once a surface of the aluminum gallium nitride layer is exposed to extend the gate recess through the scandium aluminum nitride layer.

10 . The method of claim 9 further comprising forming a gate that extends through the scandium aluminum nitride layer and is in contact with the surface of the aluminum gallium nitride layer.

11 . The method of claim 10 wherein the gate is made of metal.

12 . The method of claim 10 further comprising disposing metal contacts over the source and drain, respectively.

13 . The method of claim 10 wherein the semiconductor device is a field-effect transistor having an enhancement mode of operation.

14 . The method of claim 9 wherein the scandium aluminum nitride layer is made of Sc x Al (1-x) N with x being between 0.1 and 0.3.

15 . The method of claim 9 wherein the aluminum gallium nitride layer is made of Al y Ga (1-y) N with y being between 0.05 and 0.4.

16 . The method of claim 9 wherein the hard mask is made of a nitride compound.

17 . The method of claim 16 wherein the nitride compound is silicon nitride.

18 . The method of claim 9 wherein the hard mask is made of an oxide compound.

19 . The method of claim 18 wherein the oxide compound is silicon oxide.

20 . The method of claim 9 wherein the wet etching is performed using a mixture of sulfuric acid and hydrogen peroxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2023
From: XIE, JINQIAO; BEAM, EDWARD A., III
To: QORVO US, INC.
Reel/Frame 062513/0164 →
Continuity (2)
Provisional Application 63061823 · Aug 6, 2020
Related Publication 20230290834A1 · Sep 14, 2023
References Cited (12)
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