Systems and methods for clock synchronization using special physical layer clock sync symbols
Systems and methods for clock synchronization are disclosed in which a primary node generates special physical laver clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.
1 . A method of clock synchronization, comprising:
entering, by the primary node, into a first operating mode with respect to a secondary node;
generating, by a primary node, a clock sync symbol based on an output of a reference clock of the primary node;
generating, by the primary node, a symbol stream for transmission over a data connection to the secondary node, wherein the generated symbol stream includes a plurality of symbol encoded frames, the generated symbol stream further including one or more control symbols located between any two consecutive symbol encoded frames;
inserting, by the primary node operating in the first operating mode, the clock sync symbol at any arbitrary symbol location between any two consecutive symbol encoded frames within the generated symbol stream; and
transmitting, by the primary node operating in the first operating mode, the generated symbol stream including the inserted clock sync symbol over the data connection to the secondary node;
receiving, by the primary node operating in the first operating mode, a positive acknowledgment of the clock sync symbol from the secondary node;
switching, by the primary node, from the first operating mode into a second operating mode in response to receiving the positive acknowledgment of the clock sync symbol from the secondary node;
generating and inserting, by the primary node operating in the second operating mode, further clock sync symbols at arbitrary symbol locations within further symbol streams for transmission over the data connection to the secondary node.
2 . The method of claim 1 , wherein the primary node operating in the first operating mode inserts the clock sync symbol by replacing at least one of the control symbols between the two consecutive symbol encoded frames with the clock sync symbol.
3 . The method of claim 1 , wherein the primary node operating in the second operating mode adds at least one of the further clock sync symbols is added between two consecutive symbols of a symbol encoded frame without recalculating an error-detecting code of the symbol encoded frame.
4 . The method of claim 1 , wherein the primary node operating in the second operating mode inserts at least one of the further clock sync symbols at a symbol location adjacent to a start of a symbol encoded frame or adjacent to an end of the symbol encoded frame.
5 . The method of claim 2 , wherein transmission of the at least one control symbol replaced by the clock sync symbol is suppressed at the arbitrary symbol location between the two consecutive symbol encoded frames.
6 . The method of claim 1 , further comprising:
receiving, by the secondary node, the symbol stream from the data connection;
extracting, by the secondary node, the clock sync symbol from the symbol stream;
synchronizing, by the secondary node, a local clock of the secondary node to the reference clock of the primary node based on the extracted clock sync symbol; and
transmitting, by the secondary node, the positive acknowledgment of the clock sync symbol back to the primary node.
7 . The method of claim 6 , wherein synchronizing the local clock of the secondary node with the reference clock of the primary node comprises:
generating a sync pulse;
determining a phase error between the sync pulse and a clock pulse of the local clock; and
adjusting a phase of a next clock pulse of the local clock based on the determined phase error.
8 . The method of claim 7 , wherein generating the sync pulse comprises adjusting a phase of the sync pulse based on a transmit latency associated with the data connection.
9 . The method of claim 6 , wherein the clock sync symbol encodes time information based on an output of the reference clock, and wherein synchronizing the local clock of the secondary node to the reference clock of the primary node comprises adjusting a local time counter based on the time information encoded in the clock sync symbol.
10 . The method of claim 9 , wherein adjusting the local time counter of the local clock comprises adding or skipping one or more clock ticks to the local time counter.
11 . The method of claim 9 , wherein the time information includes a reference timestamp and wherein adjusting the local time counter of the local clock comprises overwriting the local time counter with the reference timestamp.
12 . The method of claim 11 , further comprising further adjusting the local time counter based on the reference timestamp and a transmit latency associated with the data connection.
13 . The method of claim 1 , wherein the clock sync symbol is at least one of a 64/66 bit encoded symbol and an 8/10 bit encoded symbol.
14 . The method of claim 9 , wherein the local time counter of the local clock is synchronized to have a clock tick accuracy in a range of zero to ten clock ticks of a reference time counter of the reference clock.
15 . The method of claim 1 , further comprising:
generating, by a backup primary node, a backup clock sync symbol based on an output of a reference clock of the backup primary node;
generating, by the backup primary node, another symbol stream for transmission over another data connection to the secondary node; and
inserting, by the backup primary node, the backup clock sync symbol at any arbitrary symbol location within the other symbol stream during transmission over the other data connection.
16 . The method of claim 15 , further comprising:
receiving, by the secondary node, the clock sync symbol from the primary node and the backup clock sync symbol from the backup primary node; and
synchronizing, by the secondary node, a local clock of the secondary node using one of the clock sync symbol and the backup clock sync symbol that is selected based on preconfigured priorities of the primary node and the backup primary node.
17 . The method of claim 2 , wherein the at least one control symbol that is replaced by the clock sync symbol is any of an idle symbol or a comma symbol.
18 . The method of claim 1 , wherein at least one of the further clock sync symbols are added between two consecutive symbols of a symbol encoded frame.
19 . The method of claim 1 , further comprising:
determining, by the primary node operating in the second operating mode, whether a maximum number of positive acknowledgements for the further clock sync symbols have not been received from the secondary node; and
switching, by the primary node, from the second operating mode back to the first operating mode in response to determining that the maximum number of positive acknowledgements for the further clock sync symbols have not been received from the secondary node.
20 . The method of claim 1 , wherein the primary node operating in the first operating mode with respect to the secondary node performs physical layer processing according to a first physical layer protocol specification, and wherein the primary node operating in the second operating mode with respect to the secondary node performs physical layer processing according to a second physical layer protocol specification.
21 . A clock synchronization system, comprising:
a primary node comprising a reference clock and a processor that executes a transmit engine, wherein the transmit engine operates in any of a first operating mode and a second operating mode with respect to a secondary node,
when operating in the first operating mode, the transmit engine is executed to generate a clock sync symbol from an output of the reference clock, generate a symbol stream that includes a plurality of symbol encoded frames and one or more control symbols located between any two consecutive symbol encoded frames, insert the clock sync symbol at any arbitrary symbol location between any two consecutive symbol encoded frames within the generated symbol stream, and transmit the generated symbol stream including the inserted clock sync symbol over a data connection to a secondary node,
in response to the transmit engine receiving a positive acknowledgement of the clock sync symbol from the secondary node, the transmit engine switches from the first operating mode into the second operating mode,
when operating in the second operating mode, the transmit engine is executed to generate and insert further clock sync symbols at arbitrary symbol locations within further symbol streams for transmission over the data connection to the secondary node.
22 . The clock synchronization system of claim 21 , wherein the transmit engine operating in the first operating mode inserts the clock sync symbol by replacing at least one of the control symbols between the two consecutive symbol encoded frames with the clock sync symbol.
23 . The clock synchronization system of claim 21 , wherein the transmit engine operating in the second operating mode inserts at least one of the further clock sync symbols at a symbol location adjacent to a start of a symbol encoded frame or adjacent to an end of the symbol encoded frame.
24 . The clock synchronization system of claim 22 , wherein the transmit engine suppresses transmission of the at least one control symbol replaced by the clock sync symbol at the arbitrary symbol location between the two consecutive symbol encoded frames.
25 . The clock synchronization system of claim 21 , further comprising:
a secondary node comprising a local clock and a processor that executes a receive engine,
wherein the receive engine is executed to receive the symbol stream from the data connection, extract the clock sync symbol from the symbol stream, and synchronize the local clock of the second node with the reference clock of the primary node based on the extracted clock sync symbol, and transmit the positive acknowledgment of the clock sync symbol back to the primary node.
26 . The clock synchronization system of claim 25 , wherein to synchronize the local clock of the secondary node with the reference clock of the primary node, the receive engine generates a sync pulse, determines a phase error between the sync pulse and a clock pulse of the local clock, and adjusts a phase of a next clock pulse of the local clock based on the determined phase error.
27 . The clock synchronization system of claim 26 , wherein the receive engine adjusts a phase of the sync pulse based on a transmit latency associated with the data connection.
28 . The clock synchronization system of claim 25 , wherein the clock sync symbol encodes time information based on an output of the reference clock, and wherein the receive engine adjusts a local time counter of the local clock based on the time information encoded in the clock sync symbol.
29 . The clock synchronization system of claim 28 , wherein the local time counter of the local clock is adjusted by adding or skipping one or more clock ticks.
30 . The clock synchronization system of claim 28 , wherein the time information includes a reference timestamp and wherein the local time counter is adjusted by overwriting the local time counter with the reference timestamp.
31 . The clock synchronization system of claim 30 , wherein the receive engine further adjusts the local timestamp of the local clock based on the reference timestamp and a transmit latency associated with the data connection.
32 . The clock synchronization system of claim 21 , wherein the clock sync symbol is at least one of a 64/66 bit encoded symbol and an 8/10 bit encoded symbol.
33 . The clock synchronization system of claim 25 , wherein the transmit engine is a modified physical coding sublayer (PCS) transmit engine and the receive engine is a modified PCS receive engine.
34 . The clock synchronization system of claim 22 , wherein the at least one control symbol that is replaced by the clock sync symbol is any of an idle symbol or a comma symbol.
35 . The clock synchronization system of claim 21 , wherein at least one of the further clock sync symbols are added between two consecutive symbols of a symbol encoded frame.
36 . The clock synchronization system of claim 21 , wherein the transmit engine is further executed to switch from the second operating mode back to the first operating mode in response to determining that a maximum number of positive acknowledgements for the further clock sync symbols have not been received from the secondary node.
37 . The clock synchronization system of claim 21 , wherein the transmit engine operating in the first operating mode with respect to the secondary node performs physical layer processing according to a first physical layer protocol specification, and wherein the primary node operating in the second operating mode with respect to the secondary node performs physical layer processing according to a second physical layer protocol specification.