Server power-down detection method and system, device, and medium

1. A server power-down detection method, comprising following steps:

in response to a completion of hardware power on, controlling a platform controller hub (PCH) to read BIOS (Basic Input Output System) codes from a BIOS flash memory via a first interface and running the BIOS codes;

detecting whether bits of a register of the PCH have been set;

in response to the bits of the register of the PCH being set, controlling the PCH to send power-down completion information to a BMC (Baseboard Management Controller) via a second interface; and

in response to the BMC receiving the power-down completion information, recording the power-down completion information in a BMC flash memory, and performing the hardware power on again until a test is completed.

2. The method according to claim 1 , further comprising:

in response to the completion of the hardware power on, reading BMC codes from the BMC flash memory and running the BMC codes.

3. The method according to claim 1 , further comprising:

in response to a stop in a test process, checking whether the power-down completion information is present in the BMC.

4. The method according to claim 3 , further comprising:

in response to an absence of the power-down completion information in the BMC, prolonging an interval time for power down.

5. The method according to claim 1 , wherein the step of performing the hardware power on again until the test is completed comprises:

incrementing a number of tests by one, determining whether the number of tests reaches a first threshold value, and determining, based on a determination result, whether to return to or complete the test.

6. The method according to claim 1 , wherein the step of controlling the PCH to read the BIOS codes from the BIOS flash memory via the first interface and running the BIOS codes comprises:

controlling the PCH to read the BIOS codes from the BIOS flash memory via the first interface, and to transmit the BIOS codes to a CPU (Central Processing Unit) via a third interface for running.

7. The method according to claim 1 , further comprising:

giving an alarm in response to a duration in which the bits of the register of the PCH have not been set exceeding a second threshold value.

8. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the at least one processor, wherein the at least one processor, upon execution of the computer instructions, is configured to:

in response to a completion of hardware power on, control a platform controller hub (PCH) to read BIOS (Basic Input Output System) codes from a BIOS flash memory via a first interface and running the BIOS codes;

detect whether bits of a register of the PCH have been set;

in response to the bits of the register of the PCH being set, control the PCH to send power-down completion information to a BMC (Baseboard Management Controller) via a second interface; and

in response to the BMC receiving the power-down completion information, record the power-down completion information in a BMC flash memory, and perform the hardware power on again until a test is completed.

9. The computer device according to claim 8 , wherein the at least one processor, upon execution of the computer instructions, is further configured to:

in response to the completion of the hardware power on, read BMC codes from the BMC flash memory and run the BMC codes.

10. The computer device according to claim 8 , wherein the at least one processor, upon execution of the computer instructions, is further configured to:

in response to a stop in a test process, check whether the power-down completion information is present in the BMC.

11. The computer device according to claim 10 , wherein the at least one processor, upon execution of the computer instructions, is further configured to:

in response to an absence of the power-down completion information in the BMC, prolong an interval time for power down.

12. The computer device according to claim 8 , wherein the at least one processor, upon execution of the computer instructions, is further configured to:

increment a number of tests by one, determine whether the number of tests reaches a first threshold value, and determine, based on a determination result, whether to return to or complete the test.

13. The computer device according to claim 8 , wherein the at least one processor, upon execution of the computer instructions, is further configured to:

control the PCH to read the BIOS codes from the BIOS flash memory via the first interface, and to transmit the BIOS codes to a CPU (Central Processing Unit) via a third interface for running.

14. The computer device according to claim 8 , wherein the at least one processor, upon execution of the computer instructions, is further configured to:

give an alarm in response to a duration in which the bits of the register of the PCH have not been set exceeding a second threshold value.

15. A non-transitory computer-readable storage medium storing a computer program, wherein the computer program, upon execution by a processor, is configured to cause the processor to:

in response to a completion of hardware power on, control a platform controller hub (PCH) to read BIOS (Basic Input Output System) codes from a BIOS flash memory via a first interface and running the BIOS codes;

detect whether bits of a register of the PCH have been set;

in response to the bits of the register of the PCH being set, control the PCH to send power-down completion information to a BMC (Baseboard Management Controller) via a second interface; and

in response to the BMC receiving the power-down completion information, record the power-down completion information in a BMC flash memory, and perform the hardware power on again until a test is completed.

16. The non-transitory computer-readable storage medium according to claim 15 , wherein the computer program, upon execution by the processor, is further configured to cause the processor to:

in response to the completion of the hardware power on, read BMC codes from the BMC flash memory and run the BMC codes.

17. The non-transitory computer-readable storage medium according to claim 15 , wherein the computer program, upon execution by the processor, is further configured to cause the processor to:

in response to a stop in a test process, check whether the power-down completion information is present in the BMC.

18. The non-transitory computer-readable storage medium according to claim 17 , wherein the computer program, upon execution by the processor, is further configured to cause the processor to:

in response to an absence of the power-down completion information in the BMC, prolong an interval time for power down.

19. The non-transitory computer-readable storage medium according to claim 15 , wherein the computer program, upon execution by the processor, is further configured to cause the processor to:

increment a number of tests by one, determine whether the number of tests reaches a first threshold value, and determine, based on a determination result, whether to return to or complete the test.

20. The non-transitory computer-readable storage medium according to claim 15 , wherein the computer program, upon execution by the processor, is further configured to cause the processor to:

control the PCH to read the BIOS codes from the BIOS flash memory via the first interface, and to transmit the BIOS codes to a CPU (Central Processing Unit) via a third interface for running.