Shared memory management method and device

1. A method for managing a shared memory, comprising:

setting one core of a system to be a master core, and setting remaining cores to be slave cores; applying, by the master core, to the system for a threshold quantity of idle hugepage blocks, mapping all of the idle hugepage blocks to a virtual address space of the master core, and sorting the hugepage blocks in an ascending order of physical address size of the hugepage blocks;

dividing, according to whether the physical addresses are continuous, the hugepage blocks sorted in the ascending order into segments, and determining whether segments satisfying a memory demand of a subsystem exist among all of the segments;

in response to determining that segments satisfying the memory demand of the subsystem exist among all of the segments, sorting the segments satisfying the memory demand of the subsystem in a descending order of lengths, and re-mapping the segments sorted to obtain several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses;

in response to determining that a segment satisfying a memory demand of the system exists among the several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses, releasing hugepage blocks other than the segment satisfying the memory demand of the system; and

applying for a control plane shared memory, storing a virtual address of a data plane shared memory into a relevant data pointer of the control plane shared memory, setting a master-slave synchronization mark for initialization process, and starting up initialization of the slave cores based on the synchronization mark.

2. The method according to claim 1 , wherein the applying for a control plane shared memory, storing a virtual address of a data plane shared memory into a relevant data pointer of the control plane shared memory, setting a master-slave synchronization mark for initialization process, and starting up initialization of the slave cores based on the synchronization mark, comprises:

in response to the master-slave synchronization mark for initialization process being set, applying for a named shared memory for multi-core synchronous communication and controlling, and acquiring the virtual address of the data plane shared memory from the named shared memory;

based on a master-slave-agreed hugepage naming, opening a hugepage file created by the master core in a read-write form, and performing, according to the address of the data plane shared memory, a specified address mapping, to perform initialization; and

reporting, by setting the master-slave synchronization mark, an initialization result of the slave core to the master core.

3. The method according to claim 1 , further comprising:

in response to determining that none of the segments satisfies the memory demand of the subsystem, releasing all of the hugepage blocks;

enabling the master core to apply to the system for 2 times of the threshold quantity of idle hugepage blocks, mapping all of the idle hugepage blocks to the virtual address space of the master core, and sorting the hugepage blocks in an ascending order of the physical address size of the hugepage blocks; and

dividing, according to whether the physical addresses are continuous, the hugepage blocks sorted in the ascending order into segments, and determining whether segments satisfying the memory demand of the subsystem exist among all of the segments.

4. The method according to claim 1 , wherein the re-mapping the segments sorted to obtain several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses comprises:

acquiring a size of the segment and a size of a single hugepage block in the segment, and opening a /dev/zero file in a read-only mode;

mapping the opened file to a process virtual address space using a specifyed address, wherein the size of the mapping is the size of the segment, and determining whether the mapping succeeds;

in response to determining that the mapping succeeds, recording the address where the mapping succeeds as ADDRO, and a maximum address range currently supported; and

closing the file, and performing a specified address re-mapping on each of the hugepage blocks in the segment.

5. The method according to claim 4 , wherein the closing the file, and performing a specified address re-mapping on each of the hugepage blocks in the segment comprises:

setting a specified initial mapping address to be ADDRO, a mapping length to be a size of a single hugepage block, and an initial hugepage file to be a first hugepage file in the segment;

configuring a mapping address MAP_ADDR, a size HUGEPAGE_SIZE and the hugepage file by using the initial mapping address;

opening the hugepage file that has been configured, and mapping the hugepage file according to the mapping address and the size HUGEPAGE_SIZE;

updating the mapping address MAP_ADDR to be MAP_ADDR+HUGEPAGE_SIZE, and updating the hugepage file; and

repeating the above steps, till both of the virtual addresses and the physical addresses of the segment are continuous.

6. A device for managing a shared memory, comprising:

a memory configured to store a computer program; and

a processor, wherein the computer program, when executed by the processor, causes the processor to perform operations of:

setting one core of a system to be a master core, and setting remaining cores to be slave cores; applying, by the master core, to the system for a threshold quantity of idle hugepage blocks, mapping all of the idle hugepage blocks to a virtual address space of the master core, and sorting the hugepage blocks in an ascending order of physical address size of the hugepage blocks;

dividing, according to whether the physical addresses are continuous, the hugepage blocks sorted in the ascending order into segments, and determining whether segments satisfying a memory demand of a subsystem exist among all of the segments;

in response to determining that segments satisfying the memory demand of the subsystem exist among all of the segments, sorting the segments satisfying the memory demand of the subsystem in a descending order of lengths, and re-mapping the segments sorted to obtain several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses;

in response to determining that a segment satisfying a memory demand of the system exists among the several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses, releasing hugepage blocks other than the segment satisfying the memory demand of the system; and

applying for a control plane shared memory, storing a virtual address of a data plane shared memory into a relevant data pointer of the control plane shared memory, setting a master-slave synchronization mark for initialization process, and starting up initialization of the slave cores based on the synchronization mark.

7. The device according to claim 6 , wherein the processor is further configured for:

in response to the master-slave synchronization mark for initialization process being set, applying for a named shared memory for multi-core synchronous communication and controlling, and acquiring the virtual address of the data plane shared memory from the named shared memory;

based on a master-slave-agreed hugepage naming, opening a hugepage file created by the master core in a read-write form, and performing, according to the address of the data plane shared memory, a specified address mapping, to perform initialization; and

reporting, by setting the master-slave synchronization mark, an initialization result of the slave core to the master core.

8. The device according to claim 6 , wherein the processor is further configured for:

in response to determining that none of the segments satisfies the memory demand of the subsystem, releasing all of the hugepage blocks;

applying, by the master core, to the system for 2 times of the threshold quantity of idle hugepage blocks, mapping all of the idle hugepage blocks to the virtual address space of the master core, and sorting the hugepage blocks in an ascending order of the physical address size of the hugepage blocks; and

dividing, according to whether the physical addresses are continuous, the hugepage blocks sorted in the ascending order into segments, and determining whether segments satisfying the memory demand of the subsystem exist among all of the segments.

9. The device according to claim 6 , wherein the processor is further configured for:

acquiring a size of the segment and a size of a single hugepage block in the segment, and opening a /dev/zero file in a read-only mode;

mapping the opened file to a process virtual address space using a specifyed address, wherein the size of the mapping is the size of the segment, and determining whether the mapping succeeds;

in response to determining that the mapping succeeds, recording the address where the mapping succeeds as ADDRO, and a maximum address range currently supported; and

closing the file, and performing a specified address re-mapping on each of the hugepage blocks in the segment.

10. The device according to claim 9 , wherein the processor is further configured for:

setting a specified initial mapping address to be ADDRO, a mapping length to be a size of a single hugepage block, and an initial hugepage file to be a first hugepage file in the segment;

configuring a mapping address MAP_ADDR, a size HUGEPAGE_SIZE and the hugepage file by using the initial mapping address;

opening the hugepage file that has been configured, and mapping the hugepage file according to the mapping address and the size HUGEPAGE_SIZE;

updating the mapping address MAP_ADDR to be MAP_ADDR+HUGEPAGE_SIZE, and updating the hugepage file; and

repeating the above steps, till both of the virtual addresses and the physical addresses of the segment are continuous.

11. The method according to claim 1 , wherein the applying, by the master core, to the system for a threshold quantity of idle hugepage blocks comprises:

applying, by the master core, to a host system for sufficient idle hugepage blocks by creating a hugepage named file.

12. The method according to claim 1 , wherein a sum of the memory sizes of all of the hugepage blocks is greater than 1.5 times of the memory required by the subsystem.

13. The method according to claim 1 , wherein the segment comprises hugepage blocks having continuous physical addresses.

14. The method according to claim 1 , wherein the segment satisfying the memory demand of the system is a data plane shared memory.

15. The method according to claim 1 , wherein the data pointer of the control plane shared memory is used for indicating addresses of a to-be-processed data-buffer-region at different stages.

16. The device according to claim 6 , wherein the applying, by the master core, to the system for a threshold quantity of idle hugepage blocks comprises:

applying, by the master core, to a host system for sufficient idle hugepage blocks by creating a hugepage named file.

17. The device according to claim 6 , wherein a sum of the memory sizes of all of the hugepage blocks is greater than 1.5 times of the memory required by the subsystem.

18. The device according to claim 6 , wherein the segment comprises hugepage blocks having continuous physical addresses.

19. The device according to claim 6 , wherein the segment satisfying the memory demand of the system is a data plane shared memory.

20. A non-transient computer-readable storage medium, wherein the computer-readable storage medium is stored with a program for managing a shared memory that, when executed by a processor, causes the processor to perform operations of:

setting one core of a system to be a master core, and setting remaining cores to be slave cores; applying, by the master core, to the system for a threshold quantity of idle hugepage blocks, mapping all of the idle hugepage blocks to a virtual address space of the master core, and sorting the hugepage blocks in an ascending order of physical address size of the hugepage blocks;

dividing, according to whether the physical addresses are continuous, the hugepage blocks sorted in the ascending order into segments, and determining whether segments satisfying a memory demand of a subsystem exist among all of the segments;

in response to determining that segments satisfying the memory demand of the subsystem exist among all of the segments, sorting the segments satisfying the memory demand of the subsystem in a descending order of lengths, and re-mapping the segments sorted to obtain several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses;

in response to determining that a segment satisfying a memory demand of the system exists among the several segments having both continuous intra-segment virtual addresses and continuous intra-segment physical addresses, releasing hugepage blocks other than the segment satisfying the memory demand of the system; and

applying for a control plane shared memory, storing a virtual address of a data plane shared memory into a relevant data pointer of the control plane shared memory, setting a master-slave synchronization mark for initialization process, and starting up initialization of the slave cores based on the synchronization mark.