Granted Patent B2

US 12,459,001 · App. 18/037,159 · Granted Nov 4, 2025

Inventors: Michael Kraft (Raeren, DE); Robert Puers (Blanden, BE); Sina Sadeghpour Shamsabadi (Lubbeek, BE)

Assignee: KATHOLIEKE UNIVERSITEIT LEUVEN

B06B1/0292B06B1/0666

Abstract

Claims (47)

1 . An ultrasonic transducer multilayer structure, comprising:

a semiconductor layer stack defining a diode,

a micro-machined ultrasonic transducer, MUT, layer stack being electrically in series with said diode and comprising a first electrically conductive layer, said MUT layer stack disposed at least partly on said diode,

a cavity extending over a region comprising at least a portion of said semiconductor layer stack and said first electrically conductive layer,

wherein said MUT layer stack comprises a membrane extending at least partly over said region.

2 . The ultrasonic transducer multilayer structure according to claim 1 , further comprising:

a first substrate structure for supporting the multilayer structure;

a first electrically non-conductive layer and a second electrically non-conductive layer being part of the MUT layer stack;

wherein said cavity is a cMUT closed cavity defined by the first electrically conductive layer, the first electrically non-conductive layer and the second electrically non-conductive layer and

wherein a first electrode is disposed on at least a portion of the second electrically non-conductive layer within said region; and wherein a second electrode is disposed in a recess of the semiconductor layer stack.

3 . The ultrasonic transducer multilayer structure according to claim 1 , further comprising:

a second substrate structure for supporting the multilayer structure;

a first semiconductor layer of the semiconductor layer stack being weakly doped with a dopant of a first conductivity type;

a second layer being a semiconductor layer being substrate doped with a dopant of the first conductivity type, at least 10 2 times less than the dopant concentration of the first semiconductor layer, or an isolation layer;

a third semiconductor layer of the semiconductor layer stack being heavily doped with a dopant of the first conductivity type;

wherein said cavity is a pMUT cavity defined by said second substrate structure and said region comprising at least said portion of said semiconductor layer stack and said first electrically conductive layer;

wherein said MUT layer stack comprises a piezoelectric layer; and

wherein a first portion of the first electrically conductive layer is sandwiched between the first semiconductor layer and at least a portion of the piezoelectric layer within said region, and

wherein a second portion of the first electrically conductive layer is disposed on at least a part of the second semiconductor layer such that the first portion and the second portion of the first electrically conductive layer define a first electrically conductive layer gap; and

wherein the first semiconductor layer is sandwiched between at least a part of the third semiconductor layer and the first portion of the first electrically conductive layer within said region.

4 . The ultrasonic transducer multilayer structure according to claim 3 , further comprising a fourth semiconductor layer of the semiconductor layer stack being heavily doped with a dopant of a second conductivity type,

wherein the fourth semiconductor layer is sandwiched between the first semiconductor layer and the first portion of the first electrically conductive layer within said region.

5 . The ultrasonic transducer multilayer structure according to claim 3 , further comprising a second electrically conductive layer sandwiched outside said region between the second substrate structure and the semiconductor layer stack.

6 . The ultrasonic transducer multilayer structure according to claim 3 , wherein the cavity is closed.

7 . The ultrasonic transducer multilayer structure according to claim 2 , wherein the first or second substrate structure includes one or more of a silicon wafer, a silicon-on-insulator, SOI, wafer, a silicon or SOI wafer with integrated circuitry, a semiconductor substrate, and a glass or polymer substrate with or without a thin film transistor, TFT, circuitry.

8 . The ultrasonic transducer multilayer structure according to claim 1 , further comprising:

a third substrate structure for supporting the multilayer structure;

a first semiconductor layer of the semiconductor layer stack being weakly doped with a dopant of a first conductivity type;

a second layer being an isolation layer;

a third semiconductor layer of the semiconductor layer stack being heavily doped with a dopant of the first conductivity type;

wherein said cavity is a pMUT cavity defined by said third substrate structure and said region comprising at least said portion of said semiconductor layer stack and said first electrically conductive layer;

wherein said MUT layer stack comprises a piezoelectric layer and one or more further electrically conductive layers; and

wherein a first portion of the first electrically conductive layer is sandwiched between at least a portion of the piezoelectric layer within said region and a mechanical layer being a semiconductor layer being substrate doped with a dopant of the first conductivity type or a further isolation layer, and

wherein a second portion of the first electrically conductive layer is disposed on said mechanical layer such that the first portion and the second portion of the first electrically conductive layer define a first electrically conductive layer gap.

9 . The ultrasonic transducer multilayer structure according to claim 8 , further comprising a fourth semiconductor layer of the semiconductor layer stack being heavily doped with a dopant of a second conductivity type,

wherein the fourth semiconductor layer is sandwiched between the first semiconductor layer and the first portion of the first electrically conductive layer within said region.

10 . The ultrasonic transducer multilayer structure according to claim 1 , wherein the diodes are provided by field-effect transistors.

11 . An ultrasonic transducer array device comprising a plurality of ultrasonic transducer multilayer structures as in claim 1 .

12 . A method of manufacturing an ultrasonic transducer multilayer structure according to claim 1 , comprising the steps of:

providing a first wafer according to an array configuration, wherein the first wafer defines a semiconductor layer stack, said semiconductor layer stack defining a diode;

providing a second wafer;

bonding the first wafer to the second wafer, defining a silicon-on-insulator, SOI, wafer wherein the second wafer defines a buried oxide, BOX, layer of the SOI wafer;

processing the first wafer to a predetermined thickness of the ultrasonic transducer multilayer structure;

fabricating a MUT layer stack on the diode, said MUT layer stack comprising a first electrically conductive layer;

creating a cavity extending over a region comprising at least a portion of said semiconductor layer stack and said first electrically conductive layer.

13 . Use of an ultrasonic transducer multilayer structure according to claim 1 in a sensor apparatus for measuring at least one characteristic of an object,

wherein the sensor apparatus is used for medical imaging, such as cardiac imaging, obstetrics, gynecology, abdominal imaging, intravascular imaging, and mammography, or non-destructive testing, NDA, fingerprint sensors, range finders, gesture recognition, ultrasonic haptic feedback, ultrasonic communication or MEMs speakers.

Assignments (1)

Priority Claims (3)

Continuity (1)

References Cited (33)